Abstract: This disclosure describes multiplexed optical transceivers, such as DWDM multiplexer/demultiplexers, which are aggregated in a server chassis to establish a fabric topology interconnecting blade servers to a dedicated switch module. Blade servers installed in the server chassis can utilize not just Ethernet interfaces to connect to network segments, but also PCIe interfaces as well as a combination of Ethernet and PCIe interfaces. The aggregated optical transceivers multiplex and demultiplex wavelength-specific optical signals using a laser source, reducing power consumption over switched fabric ASICs. Servicing of the multiplexed optical transceivers is facilitated by installation and replacement of a laser source. Scaling and redundancy of fabric topology interconnects can be facilitated by selection of laser sources generating expanded ranges of discrete wavelengths.

Abstract: Techniques and structures have been developed for providing lead-free column grid array interconnect structures. An exemplary interconnect has a body, a first joint, and a second joint, all having compositions off the eutectic composition in a ternary alloy system, the first joint having a ternary composition distinct from the body composition, and the second joint having a ternary composition distinct from the body composition and the first joint composition. The interconnect may be formed by solidifying a solder, having a Sn-poor ternary composition in the Sn—Ag—Cu alloy system, in contact with a column, having a Ag-rich Cu-deficient composition in the same system, and a bonding pad or bare substrate. A second solder, having a Sn-rich ternary composition, may be solidified in contact with the column and a second bonding pad or bare substrate. In some embodiments joints may be severed and reformed by remelting and resolidifying the lower-liquidus solder.

Abstract: A mechanism is disclosed for determining an accelerated test for a device. The method comprises calculating an estimated amount of damage that an element of the device would suffer if the device were operated under a set of specified conditions over a certain period of time (e.g., expected lifetime of the device). The method further comprises determining an accelerated test to which to subject the element in order to cause the element to suffer an actual amount of damage that is approximately equal to the estimated amount of damage. The accelerated test may be an accelerated test cycle, such as an accelerated temperature cycle.

Abstract: A mechanism is disclosed for determining an accelerated test for a device. The method comprises calculating an estimated amount of damage that an element of the device would suffer if the device were operated under a set of specified conditions over a certain period of time (e.g., expected lifetime of the device). The method further comprises determining an accelerated test to which to subject the element in order to cause the element to suffer an actual amount of damage that is approximately equal to the estimated amount of damage. The accelerated test may be an accelerated test cycle, such as an accelerated temperature cycle.

Abstract: An apparatus and method for connecting one substrate, such as a semiconductor die, to an opposing substrate, such as a semiconductor package or circuit board, through a plurality of intermediate thermal compensator devices, each of which can incrementally and/or locally mitigate the stresses imposed by differences in the two substrate's thermal expansion characteristics. The compensator devices can be coupled to one another, with the resulting assembly attached to the first substrate on one side, and to the second substrate on the other side, through solder bump attach, or some equivalent method. The method of the invention provides electrical connection and thermal dissipation between the two substrates as well as providing mechanical protection by absorbing the stresses imposed by the difference in thermal expansion characteristics of the two substrates.

Abstract: Techniques have been developed to provide, in some embodiments, an attachment structure for mechanically and electrically connecting substrates that is robust to differences in coefficients of thermal expansion. In some realizations lead-free alloy columns are joined to bonding pads on electronic packages having relatively low coefficients of thermal expansion (CTEs) using Pb-free solder from the same alloy system. In some embodiments, a thermal hierarchy in the tin-silver-copper (Sn—Ag—Cu or SAC) ternary alloy system is provided. In some embodiments an attachment system with a high-liquidus alloy column, an intermediate-liquidus solder, and a low-liquidus solder, all three of which components have compositions in the SAC alloy system, is provided.

Abstract: Techniques and structures have been developed for providing lead-free column grid array interconnect structures. An exemplary interconnect has a body, a first joint, and a second joint, all having compositions off the eutectic composition in a ternary alloy system, the first joint having a ternary composition distinct from the body composition, and the second joint having a ternary composition distinct from the body composition and the first joint composition. The interconnect may be formed by solidifying a solder, having a Sn-poor ternary composition in the Sn—Ag—Cu alloy system, in contact with a column, having a Ag-rich Cu-deficient composition in the same system, and a bonding pad or bare substrate. A second solder, having a Sn-rich ternary composition, may be solidified in contact with the column and a second bonding pad or bare substrate. In some embodiments joints may be severed and reformed by remelting and resolidifying the lower-liquidus solder.

Abstract: The present application describes a method and an apparatus for characterizing a conductive plane using multipoint measurement. In an embodiment of the present invention, a known current is injected in the conductive plane using multipoint probes and voltage is measured using multipoint probes. The electrical characteristics of the plane can be determined using the values of the known current, measured voltage and the distance between the probes. In an embodiment of the present invention, the conductive plane is integrated in a semiconductor package of an integrated circuit and the value of the known current is determined based on the actual current that can be provided by the integrated circuit during normal operation.

Abstract: The present application describes a method and an apparatus for characterizing a conductive plane using multipoint measurement. In an embodiment of the present invention, a known current is injected in the conductive plane using multipoint probes and voltage is measured using multipoint probes. The electrical characteristics of the plane can be determined using the values of the known current, measured voltage and the distance between the probes. In an embodiment of the present invention, the conductive plane is integrated in a semiconductor package of an integrated circuit and the value of the known current is determined based on the actual current that can be provided by the integrated circuit during normal operation.

Abstract: A method and system providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expos at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Abstract: A capacitor, including a substrate, a first interconnect layer disposed upon the substrate and a first insulating layer disposed on the first interconnect layer. A first metal layer is disposed on the first insulating layer and formed as at least two regions, the at least two regions of the first metal layer connected to the first interconnect layer through vias. A second insulating layer is disposed on the first metal layer. A second metal layer is disposed on the second insulating layer and is formed as at least two regions. The capacitor further includes a third insulating layer disposed on the second metal layer, a second interconnect layer disposed on the third insulating layer and connecting to the at least two regions of the second metal layer through vias. Finally, a first terminal is connected to the first interconnect layer and a second terminal is connected to the second interconnect layer.

Abstract: A method for providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expose at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Abstract: Systems for controlling the current consumption of an integrated circuit chip and the like so as to reduce the inductive voltage drops occurring over the power supply lines within the chip and power supply lines to the chip are disclosed. The systems according to the present invention are applicable to circuits having two or more sub-circuits formed on a semiconductor substrate, each sub-circuit having two or more power supply inputs. An exemplary system comprises two or more current shunting elements formed on the substrate, with each current shunting element coupled in parallel with the power supply inputs of a selected sub-circuit. The system has at least two main power supply lines formed on the semiconductor substrate, with each selected sub-circuit having each of its power supply inputs coupled to a main power supply line. A current shunting element may comprise a Zener diode, an active shunt circuit, or equivalents thereof.

Abstract: A semiconductor device package and a method of making such a package is described. The package comprises a flexible packaging substrate having a patterned metal layer onto which a semiconductor die is attached and a patterned insulative layer attached to the metal layer. The insulative layer includes an annular epoxy-seal gap. A glob of silicone gel is deposited and cured on the die. A casting frame is connected to the metal layer of the flexible substrate on the same side as the die. A backside moisture-blocking layer of material is attached to an opposed side of the tape. The frame and the backside layer are attached to the metal layer of the flexible substrate using cross-linkable epoxy adhesives. These epoxy adhesives join through the epoxy-seal gap to define an epoxy-seal around the die. A thermoset type of molding compound is then poured into the casting frame to define a moisture resistant package body.