Patents by Inventor Bigildis Dosdos
Bigildis Dosdos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11735508Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: GrantFiled: November 4, 2021Date of Patent: August 22, 2023Assignee: SEMICONDUCTOR COMONENTS INDUTRIES, LLCInventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
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Publication number: 20220238421Abstract: A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe.Type: ApplicationFiled: January 22, 2021Publication date: July 28, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Clemens Ypil QUINONES, Bigildis DOSDOS, Jerome TEYSSEYRE, Erwin Ian Vamenta ALMAGRO, Romel N. MANATAD
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Publication number: 20220059443Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Romel MANATAD, Chung-Lin WU, Bigildis DOSDOS, Erwin Ian ALMAGRO, Maria Cristina ESTACIO
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Patent number: 11177203Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first conductive clip, where the first terminal of the inductor can be coupled with a contact pad of the first conductive clip. The second terminal of the inductor can be electrically coupled with the leadframe via a second conductive clip, where the second terminal of the inductor can be coupled with a contact pad of the second conductive clip. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: GrantFiled: February 19, 2019Date of Patent: November 16, 2021Assignee: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
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Patent number: 11075148Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.Type: GrantFiled: November 6, 2019Date of Patent: July 27, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jeffrey Peter Gambino, David T. Price, Jeffery A. Neuls, Dean E. Probst, Santosh Menon, Peter A. Burke, Bigildis Dosdos
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Patent number: 11004777Abstract: In one general aspect, an apparatus can include a leadframe including a plurality of leads configured to provide electrical connections for the apparatus. The apparatus can also include a semiconductor die disposed on the leadframe and a conductive clip electrically coupling the semiconductor die with the leadframe. The apparatus can further include a heat slug disposed on the conductive clip. The heat slug can include a thermally conductive and electrically insulative material.Type: GrantFiled: June 28, 2019Date of Patent: May 11, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome Teysseyre, Chung-Lin Wu, Bigildis Dosdos
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Publication number: 20210111106Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.Type: ApplicationFiled: November 6, 2019Publication date: April 15, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jeffrey Peter GAMBINO, David T. Price, Jeffery A. NEULS, Dean E. PROBST, Santosh MENON, Peter A. BURKE, Bigildis DOSDOS
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Publication number: 20200411421Abstract: In one general aspect, an apparatus can include a leadframe including a plurality of leads configured to provide electrical connections for the apparatus. The apparatus can also include a semiconductor die disposed on the leadframe and a conductive clip electrically coupling the semiconductor die with the leadframe. The apparatus can further include a heat slug disposed on the conductive clip. The heat slug can include a thermally conductive and electrically insulative material.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Chung-Lin WU, Bigildis DOSDOS
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Publication number: 20190181083Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first conductive clip, where the first terminal of the inductor can be coupled with a contact pad of the first conductive clip. The second terminal of the inductor can be electrically coupled with the leadframe via a second conductive clip, where the second terminal of the inductor can be coupled with a contact pad of the second conductive clip. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: ApplicationFiled: February 19, 2019Publication date: June 13, 2019Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Jerome TEYSSEYRE, Romel MANATAD, Chung-Lin WU, Bigildis DOSDOS, Erwin Ian ALMAGRO, Maria Cristina ESTACIO
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Patent number: 10256178Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads configured to be coupled with a printed circuit board. The plurality of leads can be disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate. The assembly can being mounted on the leadframe. The apparatus can further include an inductor having a first terminal and a second terminal. The first terminal of the inductor can being coupled with the leadframe via a first contact pad, and the second terminal of the inductor can be coupled with the leadframe via a second contact pad. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: GrantFiled: August 31, 2017Date of Patent: April 9, 2019Assignee: Fairchild Semiconductor CorporationInventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
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Publication number: 20180068935Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads configured to be coupled with a printed circuit board. The plurality of leads can be disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate. The assembly can being mounted on the leadframe. The apparatus can further include an inductor having a first terminal and a second terminal. The first terminal of the inductor can being coupled with the leadframe via a first contact pad, and the second terminal of the inductor can be coupled with the leadframe via a second contact pad. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: ApplicationFiled: August 31, 2017Publication date: March 8, 2018Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Jerome TEYSSEYRE, Romel MANATAD, Chung-Lin WU, Bigildis DOSDOS, Erwin Ian ALMAGRO, Maria Cristina Estacio
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Patent number: 9379045Abstract: A first embodiment is a common drain+clip 20. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframe 40 which has external source, gate and drain contacts connected to the sources, gate and common drain of the die 20. Common drain clip 50 connects the drain 30 to external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The device 80 has a top drain contact 36 that extends to the common drain 30 across the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die 80.Type: GrantFiled: September 13, 2013Date of Patent: June 28, 2016Assignee: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
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Patent number: 8723300Abstract: The multi-chip leadless module 200 has integrated circuit (IC) 150, dual n-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.Type: GrantFiled: August 13, 2012Date of Patent: May 13, 2014Assignee: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
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Publication number: 20140070392Abstract: A first embodiment is a common drain+clip 20. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframe 40 which has external source, gate and drain contacts connected to the sources, gate and common drain of the die 20. Common drain clip 50 connects the drain 30 to external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The device 80 has a top drain contact 36 that extends to the common drain 30 across the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die 80.Type: ApplicationFiled: September 13, 2013Publication date: March 13, 2014Applicant: Fairchild Semiconductor CorporationInventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
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Publication number: 20140042599Abstract: The multi-chip leadless module 200 has integrated circuit (IC) 150, dual re-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.Type: ApplicationFiled: August 13, 2012Publication date: February 13, 2014Inventors: Chung-Lin Wu, Steven Sapp, Bigildis Dosdos, Suresh Belani, Sunggeun Yoon
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Patent number: 8487371Abstract: Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance RDS(on) include using a two-metal drain contact technique. The RDS(on) is further improved by using a through-silicon-via (TSV) technique to form a drain contact or by using a copper layer closely connected to the drain drift.Type: GrantFiled: March 29, 2011Date of Patent: July 16, 2013Assignee: Fairchild Semiconductor CorporationInventors: Daniel M. Kinzer, Steven Sapp, Chung-Lin Wu, Oseob Jeon, Bigildis Dosdos
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Patent number: 8003447Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.Type: GrantFiled: December 9, 2010Date of Patent: August 23, 2011Assignee: Fairchild Semiconductor CorporationInventors: Jeongil Lee, Myoungho Lee, Bigildis Dosdos, Charles Suico, Edwin Man Fai Lee, David Chong Sook Lim, Adriano M. Vilas-Boas
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Publication number: 20110078899Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.Type: ApplicationFiled: December 9, 2010Publication date: April 7, 2011Inventors: Jeongil Lee, Myoungho Lee, Bigildis Dosdos, Charles Suico, Lee Man Fai Edwin, David Chong Sook Lim, Adriano M. Vilas-Boas
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Patent number: 7868432Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.Type: GrantFiled: February 8, 2007Date of Patent: January 11, 2011Assignee: Fairchild Semiconductor CorporationInventors: Jeongil Lee, Myoungho Lee, Bigildis Dosdos, Charles Suico, Lee Man Fai Edwin, David Chong Sook Lim, Adriano M. Vilas-Boas
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Publication number: 20090261461Abstract: Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead fingers may have a lead intrusion disposed on the external exposed lower surface of the lead finger. The lead intrusion may have a height that is about ? to about ½ the height of a lead finger, a width that is about ? to about 1/2 the width of a lead finger, and a depth that is about ¼ to about ¾ the length of the externally exposed lower surface of a lead finger. The lead intrusion increases the area on the lead finger that contacts a bond material, such as solder, and therefore increase the strength of the joint between the semiconductor package and an external surface to which the lead finger is connected (i.e., a PCB).Type: ApplicationFiled: April 16, 2008Publication date: October 22, 2009Inventors: Steven Sapp, Chung-Lin Wu, Maria Christina B. Estacio, Bigildis Dosdos, Hamza Yilmaz