Abstract: The provided is an anti-radiation low-latency chip for neural network inference acceleration. The following steps are included: deploying a neural network inference acceleration chip at a frontend of a detector, using a streaming architecture to correspond each pipeline stage to each major neural network layer, balancing a limited on-chip memory resource and support for a large-sized input, and constructing layer parallelism, channel parallelism, and convolution kernel parallelism. This application proposes to deploy an anti-radiation, low-latency, and efficient chip for convolutional neural network (CNN) inference acceleration is deployed at the frontend of the detector to improve an intelligence level of future detector hardware.

Abstract: A high-speed CMOS pixel detector is provided, which includes a plurality of super pixel modules, where each super pixel module includes an array of N×M super pixel cells and a digital readout logic circuit connected to the N×M super pixel cells, and data is output between the super pixel modules via asynchronous control logic; and peripheral modules, including at least an EoC module, a peripheral readout module, and a peripheral data transmission module connected in sequence, where the EoC module is connected to the super pixel modules. This application adopts a structure in which a plurality of super pixel cells are integrated, allowing for upgrading of a serial sparse readout mode to a parallel sparse readout mode, thereby greatly improving a readout rate, enabling a plurality of pixels to share resources, and reducing pixel dimensions.

Abstract: A high-speed CMOS pixel detector is provided, which includes a plurality of super pixel modules, where each super pixel module includes an array of N×M super pixel cells and a digital readout logic circuit connected to the N×M super pixel cells, and data is output between the super pixel modules via asynchronous control logic; and peripheral modules, including at least an EoC module, a peripheral readout module, and a peripheral data transmission module connected in sequence, where the EoC module is connected to the super pixel modules. This application adopts a structure in which a plurality of super pixel cells are integrated, allowing for upgrading of a serial sparse readout mode to a parallel sparse readout mode, thereby greatly improving a readout rate, enabling a plurality of pixels to share resources, and reducing pixel dimensions.