Patents by Inventor Bijesh Rajamohanan
Bijesh Rajamohanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10354728Abstract: After programming a set of resistive memory cells in a resistive memory device, the programmed states and the functionality of each resistive memory cell in the programmed set can be verified by a primary determination method and a secondary determination method. The primary determination method employs the step of determining whether a measured electrical current at a preset read voltage for the selected resistive memory cell is within electrical current specification for the selected resistive state. If the selected cell fails the primary determination method, the second determination method is performed, which includes determining whether a measured threshold voltage for the selected resistive memory cell is within threshold voltage specification for the selected resistive state. If the selected cell fails both methods, the selected cell is identified as a non-functional resistive memory cell. Otherwise, the selected cell is identified as an operational cell.Type: GrantFiled: June 28, 2017Date of Patent: July 16, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Bijesh Rajamohanan, Juan Pablo Saenz
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Publication number: 20190130971Abstract: Apparatuses, systems, and methods are disclosed for write-time prevention of data retention failures for non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to perform a write operation for at least one cell. A controller may be configured to identify, during a write operation, one or more cells for which a characteristic of the one or more identified cells is associated with data retention failure. A controller may be configured to modify a write operation for one or more identified cells.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Applicant: SanDisk Technologies LLCInventor: Bijesh Rajamohanan
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Patent number: 10256402Abstract: A method of operating a resistive memory device includes providing a resistive memory device including an array of resistive memory cells, where each of the resistive memory cells includes a resistive memory material having at least two different resistive states, performing a first mode read operation on a group of resistive memory cells within the array, determining a bit error rate for data generated by the first mode read operation, determining whether the determined bit error rate is below a predetermined limit, and performing a second mode read operation on the group of resistive memory cells within the array based on a threshold voltage if the determined bit error rate is above the predetermined limit.Type: GrantFiled: September 25, 2017Date of Patent: April 9, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Bijesh Rajamohanan, Juan Saenz
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Publication number: 20190097132Abstract: A method of operating a resistive memory device includes providing a resistive memory device including an array of resistive memory cells, where each of the resistive memory cells includes a resistive memory material having at least two different resistive states, performing a first mode read operation on a group of resistive memory cells within the array, determining a bit error rate for data generated by the first mode read operation, determining whether the determined bit error rate is below a predetermined limit, and performing a second mode read operation on the group of resistive memory cells within the array based on a threshold voltage if the determined bit error rate is above the predetermined limit.Type: ApplicationFiled: September 25, 2017Publication date: March 28, 2019Inventors: Bijesh RAJAMOHANAN, Juan SAENZ
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Publication number: 20190066781Abstract: A memory device is provided that includes a memory array having a plurality of reversible resistance-switching memory cells, and a memory controller coupled to the memory array. The memory controller is adapted to program a first reversible resistance-switching memory cell in the memory array to a predetermined data state, determine a program loop count associated with the program step, and retire the first reversible resistance-switching memory cell from further use for host data storage based on the associated program loop count.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Applicant: SANDISK TECHNOLOGIES LLCInventors: Bijesh Rajamohanan, Srinitya Musunuru, Emmanuelle Merced-Grafals
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Publication number: 20190006005Abstract: After programming a set of resistive memory cells in a resistive memory device, the programmed states and the functionality of each resistive memory cell in the programmed set can be verified by a primary determination method and a secondary determination method. The primary determination method employs the step of determining whether a measured electrical current at a preset read voltage for the selected resistive memory cell is within electrical current specification for the selected resistive state. If the selected cell fails the primary determination method, the second determination method is performed, which includes determining whether a measured threshold voltage for the selected resistive memory cell is within threshold voltage specification for the selected resistive state. If the selected cell fails both methods, the selected cell is identified as a non-functional resistive memory cell. Otherwise, the selected cell is identified as an operational cell.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Inventors: Bijesh Rajamohanan, Juan Pablo Saenz
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Patent number: 10008273Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.Type: GrantFiled: June 13, 2016Date of Patent: June 26, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Biswajit Ray, Gerrit Jan Hemink, Mohan Dunga, Bijesh Rajamohanan, Changyuan Chen
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Publication number: 20180138292Abstract: A method is provided that includes forming a bit line above a substrate, forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first portion disposed between a first electrode and a second electrode, the first electrode includes a first material having a first work function, the second electrode includes a second material having second work function, and the first work function does not equal the second work function.Type: ApplicationFiled: November 11, 2016Publication date: May 17, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Alvaro Padilla, Bijesh Rajamohanan
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Publication number: 20170358365Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Applicant: SanDisk Technologies LLCInventors: Biswajit Ray, Gerrit Jan Hemink, Mohan Dunga, Bijesh Rajamohanan, Changyuan Chen
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Patent number: 9837153Abstract: Technology is described for selecting a group of reversible-resistance memory cells in which to store data based on information regarding switching the reversible-resistance memory cells from a first resistance state in which the reversible-resistance memory cells are in immediately after fabrication to a second resistance state for the first time after fabrication. Information regarding switching the reversible-resistance memory cells from the first resistance state to the second resistance state for the first time after fabrication may provide insight into factors including, but not limited to, endurance and data retention. In one aspect, a control circuit is configured to select a group of reversible-resistance memory cells in which to store data based on both the difficulty in switching from the first resistance state to the second resistance state for the first time after fabrication and a temperature of the data to be stored in the memory system.Type: GrantFiled: March 24, 2017Date of Patent: December 5, 2017Assignee: Western Digital Technologies, Inc.Inventors: Bijesh Rajamohanan, Christopher Petti, Xinde Hu
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Patent number: 9805793Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.Type: GrantFiled: April 1, 2016Date of Patent: October 31, 2017Assignee: SanDisk Technologies LLCInventors: Bijesh Rajamohanan, Juan Saenz, Alvaro Padilla, Mohsen Purahmad, Ashot Melik-Martirosian
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Publication number: 20170287557Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Applicant: SanDisk Technologies Inc.Inventors: Bijesh Rajamohanan, Juan Saenz, Alvaro Padilla, Mohsen Purahmad, Ashot Melik-Martirosian