Patents by Inventor Bijit Patel

Bijit Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GATED RING OSCILLATOR LINEARIZATION
    Publication number: 20230418238
    Abstract: Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.
    Type: Application
    Filed: September 13, 2023
    Publication date: December 28, 2023
    Inventors: Marius MOE, Tarjei AABERGE, Bijit PATEL
  • Gated ring oscillator linearization
    Patent number: 11762340
    Abstract: Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: September 19, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marius Moe, Tarjei Aaberge, Bijit Patel
  • GATED RING OSCILLATOR LINEARIZATION
    Publication number: 20230031630
    Abstract: Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Inventors: Marius MOE, Tarjei AABERGE, Bijit PATEL
  • Systems and methods for ESD protection
    Patent number: 7719806
    Abstract: A negative electrostatic discharge (ESD) protection network or circuit is described. The circuit can provide protection against a negative-going ESD transient. One embodiment, along with standard positive ESD protection networks, can discharge ESD currents in both polarities and is able to tolerate a positive/negative voltage that is higher than the maximum voltage allowed for the given fabrication process. It can be used to protect an I/O pin that can be exposed to a relatively wide signal swing range.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: May 18, 2010
    Assignee: PMC-Sierra, Inc.
    Inventors: Graeme B. Boyd, Xun Cheng, Bijit Patel