Abstract: Multi-mode transceiver and a circuit for operating the multi-mode transceiver. A multi-mode transceiver includes a first circuit that is configurable to operate as one of a transmitter and a receiver in a first mode, and a second circuit that is configurable to operate as one of the transmitter and the receiver in a second mode. The multi-mode transceiver includes a first element coupled to the first circuit. The multi-mode transceiver includes a second element coupled to the first element and one or more ports. The multi-mode transceiver also includes a first switch, coupled to the second element and to the second circuit, that is configurable to operate the transceiver in at least one of the first mode and the second mode in conjunction with the first element and the second element.

Abstract: VCO frequency is continuously variable through a wide frequency range in proportion to a first control voltage VC produced by a PLL containing the VCO. A second control voltage NVC is produced as a monotonically decreasing function of VC. A first current I0 is produced in proportion to VC and a second current I1 is produced in proportion to NVC. I1 is subtracted from I0, producing a control current IC=I0-I1 which is applied to the VCO.

Abstract: A differential receiver having a precision input referred offset and a wide CMR, wherein a pair of differential-difference amplifiers are used as differential comparators. The differential-difference amplifiers are configured to allow a precision input-referred offset to be set by the use of two reference voltages. The differential comparators each have a common-mode range over a different portion of the rail-to-rail voltage range. A first one of these differential comparators is activated when the input common-mode voltage is above a threshold level. A second differential comparator is activated when the input common-mode voltage is below the threshold. The output of the differential comparator that is selected is to provide a comparison output signal, thereby achieving a wide CMR. The selection of either the first or second differential comparator is made by a selection circuit that includes a differential Schmitt Trigger and a multiplexer.

Abstract: Embodiments of the invention include an amplifier such as a differential amplifier having an improved common mode voltage range (CMVR). The amplifier includes a translator coupled to a second stage amplifying circuitry wherein the translator uses feedback and a parallel connection of input devices to improve the common mode voltage range of the amplifier while providing for enablement of the circuit functionality. The translator uses parallel connections of N-channel and P-channel devices such as transistors to extract alternating current (ac) signals riding on a common mode voltage and to translate the extracted ac signals to ride on a constant reference voltage (V.sub.ref). The translated signals are then amplified in a conventional manner, such as by a gate thresholding or a self-biasing technique. An input sensing circuit within the translator provides an offset detection signal to a correction circuit, also within the translator.

Abstract: A low voltage CMOS input buffer protection circuit that is used to protect an input buffer from any high voltage signal (e.g., 5 V) that may appear along a signal bus. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). The circuit includes a CMOS transmission gate and utilizes on-chip generated reference voltages to provide the necessary protection.

Abstract: A CMOS high voltage drive output buffer that protects the drive stage from seeing relatively high voltages (e.g., 5 V) during "hot pluggable" conditions (that is, when the reference voltage VDD is not present). A transmission gate and clamping transistors are disposed around the output devices to provide the requisite protection. A backgate bias generator for use with P-channel devices is also disclosed that is capable of withstanding "hot pluggable" conditions.

Abstract: An integrated, low power bus holder circuit implemented in low voltage technology is capable of interfacing with a relatively high voltage bus. In an illustrative embodiment, the bus holder circuit includes a first inverter for inverting a logic voltage present on a data bus and a second inverter for inverting the output of the first inverter. The second inverter is comprised of a series string of first and second pFETS and first and second nFETS, with the gates of the first pFET and first nFET coupled to the output of the first inverter. The data bus is coupled to a first circuit node between the second nFET and second pFET, and the bus logic level is maintained thereat. A third pFET is coupled to the second inverter and conducts current when a high logic voltage is present on the bus. A resistance device is coupled between a drain of the third pFET and a point of low reference potential.

Abstract: A current output circuit comprises a current driver that is switchably connected across two output nodes by a switching assembly and having a switchable shunt resistor connected across the current driver. The switchable shunt resistor may be switched between a non-conducting state and a resistive conducting state. In a first data state, the current driver is connected to the output nodes by the switching assembly and the switchable shunt resistor is non-conducting so that the supplied current will flow through a load attached to the output nodes. In a second data state, the current driver is disconnected from the output nodes and the switchable shunt resistor is in a resistive conducting state. In this state the current bypasses the load and is diverted through the switchable shunt resistor. Several current drivers with appropriate switching arrangements and one or more switchable shunt resistors may be provided to allow for asymmetric current outputs in various data states.

Abstract: A CMOS voltage generator for providing a reference voltage VDD2 that will track the low level power supply voltage VDD (approximately 3.0V-3.6V) as long as the power supply is present. When VDD is not present (defined as at "hot pluggable" condition), the voltage generator is configured to maintain a "protection" output voltage less than the relatively high voltage (approximately 5V) that may appear along a circuit signal bus. In particular, the circuit includes at least a pair of diode-connected N-channel devices disposed between the signal bus line and the output voltage terminal to provide the necessary protection.

Abstract: A low voltage CMOS output buffer protection circuit is configured to protect an associated output buffer from any high voltage signals (e.g., 5V) that may appear along a signal bus line. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). An on-chip reference voltage generator is used to provide a reference voltage VDD2 that will be essentially equal to VDD as long as VDD is present. When VDD is not present, VDD2 will track the signal appearing along the signal bus (PAD), remaining at least two diode drops below the PAD voltage.

Abstract: An integrated circuit output buffer has an improved tolerance to voltage levels that are greater than the power supply voltage level at which the IC is designed to operate. A first transmission gate transistor (110), typically p-channel, is connected between an output conductor (101) and a resistor (108) at a given node (114). The node is also connected to the gate of a second transmission gate transistor (105), typically also p-channel. The resistor pulls the given node towards a power supply voltage level (e.g., ground), so that the second transmission gate transistor conducts in normal operation. To prevent the node from reaching ground, at least one diode-like voltage-dropping device (201, 202) is connected in series with the resistor.

Abstract: A current source includes a first current mirror and a second current mirror that share a common current path. The current in the common current path mirrors a current of a current reference connected to the first current mirror. A current in an output current path of the second current mirror mirrors the current of the common current path. A first feedback loop controls the current in the common current path and a second feedback loop matches a voltage of the common current path with an output voltage. The cooperation of the first and second feedback loops ensures that the output current replicates the current of the current reference even when an voltage of the current source is close to the supply voltage. Thus, the voltage swing of the current source output voltage is increased and a precision current source is provided even when the output voltage is close to the supply voltage.