Abstract: One example discloses a communications system, having: a communications unit, including circuits for processing data signal frequencies; a geographic location unit having a first location signal input, triggered at a first geographic location, and a second location signal input, triggered at a second geographic location; a geographic frequency database including: a first subset of data signal frequencies which can be validated by the communications unit at the first location; and a second subset of data signal frequencies which can be validated by the communications unit at the second location; a frequency scan control unit electrically coupled to the communications unit, the geographic location unit and the geographic frequency database; and wherein the scan control unit configures the communications unit to process the first subset of communication frequencies in response to the first location trigger and to process the second subset of communication frequencies in response to the second location trigger.

Abstract: A vehicle parking assistance system is based on presenting a bird's eye view. The display has an input interface such as a touch-input display or a remote input device such as a joystick. In this case, by selecting a desired position on the display (which is presenting an image of an object or location in space for which the driver is wanting to know the range), the user is able to request a distance calculation between the vehicle and that location in space. The distance information can be provided as an audible message and/or as a visual overlay message onto the bird's eye view.

Abstract: A video processor comprises an instruction set of programmed operations for operating on video data. The instruction set has an instruction which corresponds to a programmed operation for performing a motion estimation calculation between pixel data in frames of video data. The programmed operation causes the processor to calculate a measure of motion estimation at each of a plurality of search locations within a search window. The processor comprises a plurality of calculation units (6), each of the units (6) being operable to perform a calculation, or partial calculation, at a different search location. The plurality of calculation units (6) perform the calculations, or partial calculations, in parallel. The measure of motion estimation calculation is one of: a sum of absolute difference (SAD) calculation; a mean square error (MSE) calculation, a mean absolute error (MAE) calculation.

Abstract: A data processing system is provided with at least one processing unit (1) for an interleaved processing of multiple tasks (T1-T3), and a cache (5) associated to the at least one processing unit (1) for caching data for the multiple tasks (T1-T3) to be processed by the at least one processing unit (1). The cache (5) is divided into a plurality of cache lines (6). Each of the cache lines (6) is associated to one of the multiple tasks (T1-T3). Furthermore, a task scheduler (10) is provided for scheduling the multiple tasks (T1-T3) to be processed in an interleaved manner by the at least one processing unit (1). A cache controller (20) is provided for selecting those cache lines (6) in the cache (5), which are to be evicted from the cache (5). This selection is performed based on the task scheduling of the task scheduler (10).

Abstract: A vehicle parking assistance system is based on presenting a bird's eye view. The display has an input interface such as a touch-input display or a remote input device such as a joystick. In this case, by selecting a desired position on the display (which is presenting an image of an object or location in space for which the driver is wanting to know the range), the user is able to request a distance calculation between the vehicle and that location in space. The distance information can be provided as an audible message and/or as a visual overlay message onto the bird's eye view.

Abstract: A video processor comprises an instruction set of programmed operations for operating on video data. The instruction set has an instruction which corresponds to a programmed operation for performing a motion estimation calculation between pixel data in frames of video data. The programmed operation causes the processor to calculate a measure of motion estimation at each of a plurality of search locations within a search window. The processor comprises a plurality of calculation units (6), each of the units (6) being operable to perform a calculation, or partial calculation, at a different search location. The plurality of calculation units (6) perform the calculations, or partial calculations, in parallel. The measure of motion estimation calculation is one of: a sum of absolute difference (SAD) calculation; a mean square error (MSE) calculation, a mean absolute error (MAE) calculation.

Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Abstract: The present invention proposes a method and a system for dynamic cache partitioning for application tasks in a multiprocessor. An approach for dynamically resizing cache partitions based on the execution phase of the application tasks is provided. The execution phases of the application tasks are identified and updated in a tabular form. Cache partitions are resized during a particular instance of the execution of application tasks such that the necessary and sufficient amount of cache space is allocated to the application tasks at any given point of time. The cache partition size is determined according to the working set requirement of the tasks during its execution, which is monitored dynamically or statically. Cache partitions are resized according to the execution phase of the task dynamically such that unnecessary reservation of the entire cache is avoided and hence an effective utilization of the cache is achieved.

Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Abstract: A data processing system includes processing units for processing data, at least one memory for storing data from the processing units, an interconnect for connecting the processing units and the memory. The processing units request write access to the memory via the interconnect to write data into the memory. At least one arbiter performs interconnect arbitration for the access to the memory from the processing units, wherein interconnect arbitration is performed based on the minimum logic level changes of the interconnect as introduced by the write accesses of the processing units to the memory. If more than one write request is available from different processing units the interconnect arbitration (interconnect access), is granted to that processing unit, whose data to be sent to the memory via the interconnect results in minimum logic level changes to the interconnect. Power dissipation due to switching of logic levels is reduced.

Abstract: A data processing system is provided comprising at least one processing unit for processing data; a memory means for storing data; and a cache memory means for caching data stored in the memory means. Said cache memory means is associated to at least one processing unit. An interconnect means is provided for connecting the memory means and the cache memory means. The cache memory means is adapted for performing a cache replacement based on reduced logic level changes of the interconnect means as introduced by a data transfer between the memory means and the cache memory means.

Abstract: A data processing system is provided with at least one processing unit (1) for an interleaved processing of multiple tasks (T1-T3), and a cache (5) associated to the at least one processing unit (1) for caching data for the multiple tasks (T1-T3) to be processed by the at least one processing unit (1). The cache (5) is divided into a plurality of cache lines (6). Each of the cache lines (6) is associated to one of the multiple tasks (T1-T3). Furthermore, a task scheduler (10) is provided for scheduling the multiple tasks (T1-T3) to be processed in an interleaved manner by the at least one processing unit (1). A cache controller (20) is provided for selecting those cache lines (6) in the cache (5), which are to be evicted from the cache (5). This selection is performed based on the task scheduling of the task scheduler (10).

Abstract: A data processing system comprising a plurality of processing units (Dv1-DvM) for processing data, at least one memory means (MM) for storing data from said plurality of processing units (Dv1-DvM), an interconnect means (IM) for connecting said plurality of processing units (Dv1-DvM) and said at least one memory means (MM) is provided. Said processing units (Dv1-DvM) are adapted to request a write access to said at least one memory means (MM) via the interconnect means (IM) in order to write data into said at least one memory means (MM). At least one arbiter means (AU) is provided for performing an interconnect arbitration for the access to said at least one memory means (MM) from said plurality of processing units (Dv1-DvM), wherein said interconnect arbitration is performed based on the minimum logic level changes of said interconnect means (IM) as introduced by the write accesses of said plurality of processing units (Dv1-DvM) to said at least one memory means (MM).

Abstract: A method for circularly accessing a plurality of memory addresses, using a sequence of values comprises determining a plurality of values, the number of values in the plurality of values being m, each value being represented by a predefined number of bits n. The method further comprises identifying in a register (20) of a processor, comprising a plurality of addressable bits ordered by significance, a sequence of m times n consecutive bits, thus having defined a set of m units (21, 22, 23, 24) of n consecutive bits each. It involves initializing each unit of the set of units with the bits representing a different value of the plurality of values, and rotating the identified bits of the register (20) with a number of bits equal to an integer multiple of n. The method also comprises reading a unit for obtaining a value represented by the unit.

Abstract: An electronic data processing circuit contains a plurality of data handling units (10a-d, 16a-b) with data outputs, at least part of the data handling units having address outputs. The data handling units supply words of preferably selectable size to a bus. A bus controller (20) is arranged to control access to the bus in successive access cycles. The bus controller (20) causes data bits from a plurality of data words from respective ones of the data handling units (10a-d, 16a-b), to be placed in combination on the data lines in a same bus cycle. The bus controller causes write addresses that the respective ones of the data handling units (10a-d, 16a-b) supply for respective ones of the plurality of data words to be placed on the address lines in a plurality of respective bus cycles. Preferably, the temporal or spatial arrangement of the data words on the bus lines adapted so as to minimize the number of logic level changes on the bus.

Abstract: The present invention discloses a compilation method of a program code in a digital device in a profile driven compilation. An approach for optimizing the execution of program code by providing additional intelligence to the compiler is provided, where the compiler decides whether to have single decision tree with guarded operations or multiple decision trees. The method of this invention is helpful, in reducing the overhead of conditional code branching to have an optimised program code, both in compiler driven optimisations and in manual optimisations by the programmer.

Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Abstract: A data processing system is provided comprising at least one processing unit (10) for processing data; a memory means (40) for storing data; and a cache memory means (20) for caching data stored in the memory means (40). Said cache memory means (20) is associated to at least one processing unit (10). An interconnect means (30) is provided for connecting the memory means (40) and the cache memory means (20). The cache memory means (20) is adapted for performing a cache replacement based on reduced logic level changes of the interconnect means (30) as introduced by a data transfer (DO-Dm) between the memory means (40) and the cache memory means (20).

Abstract: An electronic data processing circuit contains a plurality of data handling units (10a-d, 16a-b) with data outputs, at least part of the data handling units having address outputs. The data handling units supply words of preferably selectable size to a bus. A bus controller (20) is arranged to control access to the bus in successive access cycles. The bus controller (20) causes data bits from a plurality of data words from respective ones of the data handling units (10a-d, 16a-b), to be placed in combination on the data lines in a same bus cycle. The bus controller causes write addresses that the respective ones of the data handling units (10a-d, 16a-b) supply for respective ones of the plurality of data words to be placed on the address lines in a plurality of respective bus cycles. Preferably, the temporal or spatial arrangement of the data words on the bus lines adapted so as to minimize the number of logic level changes on the bus.