Patents by Inventor Bikash Kumar Agarwal

Bikash Kumar Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scan warmup scheme for mitigating di/dt during scan test
    Patent number: 9291676
    Abstract: We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: March 22, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Atchyuth K Gorti, Aditya Jagirdar, Bikash Kumar Agarwal, Eric Quinnell
  • Scan Warmup Scheme for Mitigating DI/DT During Scan Test
    Publication number: 20140237312
    Abstract: We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Atchyuth K. Gorti, Aditya Jagirdar, Bikash Kumar Agarwal, Eric Quinnell