Abstract: Systems and methods for propagating poison information are provided. Embodiments include receiving write data having a poison flag asserted indicating the data to be written to a memory device is erroneous. Embodiments further include converting the write data to a pre-fixed data pattern and generating a parity code, based upon, at least in part, the pre-fixed data pattern. Embodiments may also include injecting a correctable error into the write-data or parity code and writing the write data and parity code into the memory device. The correctable error injection may occur in the data or in the parity code and during the read the comparison may occur accordingly.

Abstract: A device including an address extraction for a data burst associated with a host processor and to map the data burst to a memory according to a rotation is provided. The device includes a splitter to separate a first command that associates the data burst with a first round in the rotation, and a selection logic to select, from the first round in the rotation, a first bank group at the address in the memory to execute the first command, and execution logic to receive the data burst and the address in the memory to activate the first bank group at the address in the memory, and to schedule an execution of the first command based on an availability of a second bank group from the first round in the rotation. A system and a non-transitory computer readable medium storing instructions to use the device are also provided.

Abstract: Embodiments of the invention provide an apparatus and method for a coherent, efficient, and configurable cyclic check redundancy retry implementation for synchronous dynamic random access memory. The process includes storing write commands as groups of bursts in a storage location where those commands are stored at least until a time frame has passed for receiving a corresponding cyclic redundancy check failure message. In some embodiments, the process includes retrying corresponding groups of bursts after receiving a failure message where retried groups of bursts are given priority over other memory access commands. In some embodiments, when a read command is received corresponding to a write command that is not beyond the relevant time frame the read command will also be held back from execution until the corresponding time frame has passed without notification of cyclic redundancy check value failure.

Abstract: Disclosed are peripheral component interconnect (PCI) implementations and methods for implementing PCI implementations handling posted transaction layer packets (TLPs) and completion TLPs. PCI implementations include one or more receive buffers storing completion TLPs and posted TLPs, a set of write and read pointers for the receive buffers, a token manager to associate ordering tokens with posted TLPs, and a pointer-based ordering mechanism to determine an order for handling posted and completion TLPs. PCI implementations may further include an identification-based ordering mechanism to revise the order. The methods identify a completion TLP and multiple posted TLPs, associate a posted TLP with an ordering token, and determine the order for handling the completion and posted TLPs with at least the pointer-based ordering mechanism. The methods may further optionally revise the order with at least the identification-based ordering mechanism.

Abstract: A memory controller system optimally controls access to a memory device having a plurality of integrated circuit (IC) chips disposed in a non-uniform stack configuration within a three-dimensional stacked (3DS) structure. A memory profiling portion executes to determine the non-uniform stack configuration. A virtual rank mapping portion configured to assign virtual ranks to chip locations actually defined by the non-uniform stack configuration. An address conversion portion executes to convert an unoptimized address definable with reference to a uniform stack configuration to an optimized address defined with reference to the non-uniform stack configuration. The addressing overhead during monitoring of data access operations to the memory device is optimized.

Abstract: Operation based polling in a memory system. A device manager is provided to perform efficient polling by utilizing the effective bandwidth of the memory system, in a controller coupled to a communication end point. The device manager includes a detection module for detecting a type of operation sent to the communication end point. The device manager also includes a storage module for storing a polling interval value based on a time period of the type of operation in a polling counter of the controller. Further, the device manager includes a controlling module for controlling a polling operation of the controller in such a way that the controller polls the communication end point after a wait period according to the polling interval value.

Abstract: A programmable sequence generator for controlling a flash memory device. The programmable sequence generator includes a plurality of programmable sequence registers including control phase sequence (CPS) registers and data phase sequence (DPS) registers programmed with phase sequence values corresponding to an operation command sequence of the flash memory device; and logic circuitry in a programmable command sequencer for controlling a set of states of the programmable command sequencer using the plurality of programmable sequence registers.

Abstract: A configurable and reusable hardware-software NAND system adaptive to various NAND devices independent of the NAND device manufacturer and NAND device characteristics. A device identification signature is decoded from a NAND device in a NAND system; the device identification signature signal is analyzed to obtain a control phase sequence value descriptive of a characteristic of the NAND device; the control phase register is populated with the control phase sequence value; and control phase register provides the control phase sequence values to the command sequencer. The control phase register can be programmed by a low level driver for devices which NAND system cannot decode the device identification signature.

Abstract: A programmable sequence generator for controlling a flash memory device. The programmable sequence generator includes a plurality of programmable sequence registers including control phase sequence (CPS) registers and data phase sequence (DPS) registers programmed with phase sequence values corresponding to an operation command sequence of the flash memory device; and logic circuitry in a programmable command sequencer for controlling a set of states of the programmable command sequencer using the plurality of programmable sequence registers.

Abstract: An Execute-In-Place (XIP) implementation in a NAND controller of the kind that controls a NAND flash memory device. A page load command is provided to a predefined block and page address in a NAND device and identifies whether the boot read request received from the processor is a continuation of a previous boot read request. A read enable pin in the NAND device is toggled if the boot read request is a continuation of the previous boot read request. A random data output command sequence is sent to the NAND device and the read enable pin is toggled if the boot read request is not a continuation of the previous boot read address.