Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. A designer may also designate a waiver region based on pattern matching, cell names or layout markers in which layout region one or more verification rules may be inapplicable. A waiver region identification item for the waiver region may be associated with a waiver geometric element and the one or more verification rules.

Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. A designer may also designate a waiver region based on pattern matching, cell names or layout markers in which layout region one or more verification rules may be inapplicable. A waiver region identification item for the waiver region may be associated with a waiver geometric element and the one or more verification rules.

Abstract: Contour-related information for geometric elements in layout design data is obtained. Relevant portions of the contour-related information are provided to a canonical hash function, from which a canonical signature for the layout design data is generated.

Abstract: Waiver regions may be identified by waiver identification items. The waiver identification items may be determined based on conducting a density check process. Additionally or alternatively, reference patterns for pattern matching, cell names or markers may serve as the waiver identification items. Waiver geometric items may be created for the waiver regions and added to the layout design. Based on an overlap of a density check window with the waiver geometric items and waiving threshold information, a density violation in that density check window is determined to be reported as a density violation or a waived density violation with some implementations of the invention. With some other implementations of the invention, pattern density of a density check window may not be checked if an overlap of the density check window with the waiver geometric items is above a waiving threshold value.

Abstract: The invention concerns the generation of schematics from analog netlists. Various implementations of the invention provide that an analog netlist defining a number of hardware components and the connectivity between the hardware components is identified. Subsequently, the netlist is sorted and partitioned into component groups. The component groups are arranged and lines are routed between the component groups. The corresponding hardware components are arranged within the component groups and a schematic corresponding to the arranged hardware components is generated.

Abstract: Contour-related information for geometric elements in layout design data is obtained. Relevant portions of the contour-related information are provided to a canonical hash function, from which a canonical signature for the layout design data is generated.

Abstract: Waiver regions may be identified by waiver identification items. The waiver identification items may be determined based on conducting a density check process. Additionally or alternatively, reference patterns for pattern matching, cell names or markers may serve as the waiver identification items. Waiver geometric items may be created for the waiver regions and added to the layout design. Based on an overlap of a density check window with the waiver geometric items and waiving threshold information, a density violation in that density check window is determined to be reported as a density violation or a waived density violation with some implementations of the invention. With some other implementations of the invention, pattern density of a density check window may not be checked if an overlap of the density check window with the waiver geometric items is above a waiving threshold value.

Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. A designer may also designate a waiver region based on pattern matching, cell names or layout markers in which layout region one or more verification rules may be inapplicable. A waiver region identification item for the waiver region may be associated with a waiver geometric element and the one or more verification rules.

Abstract: A method for processing machine information of a system, such as an integrated circuit design, to generate a display of a finite state machine diagram by determining a position for the states in the diagram and then showing representations of the transitions between states to create a symmetrical, compact and cyclic process view of the finite state machine. Levels are assigned to the states in a first direction. A rule based technique then is used to order the states in levels that ensure minimum crossings of transitions between consecutive levels as well as for transitions in a same level. Next, the specific position of each state in a second direction orthogonal to the first direction is computed, such that the positions take into account areas or “tracks” in which connection lines representing transitions between states will be rendered. The connection line representing transitions between states are then rendered in the diagram.

Abstract: The invention concerns the generation of schematics from analog netlists. Various implementations of the invention provide that an analog netlist defining a number of hardware components and the connectivity between the hardware components is identified. Subsequently, the netlist is sorted and partitioned into component groups. The component groups are arranged and lines are routed between the component groups. The corresponding hardware components are arranged within the component groups and a schematic corresponding to the arranged hardware components is generated.