Patents by Inventor Bilal Ahmad Janjua

Bilal Ahmad Janjua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10902926
    Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: January 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sun Min, Vivek Venkata Kalluru, Tae-hong Kwon, Ki-won Kim, Sung-whan Seo, Bilal Ahmad Janjua
  • Publication number: 20210005253
    Abstract: A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current.
    Type: Application
    Filed: April 13, 2020
    Publication date: January 7, 2021
    Inventors: JI-HOON LIM, BILAL AHMAD JANJUA
  • Patent number: 10867673
    Abstract: A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.
    Type: Grant
    Filed: August 17, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bilal Ahmad Janjua, Vivek Venkata Kalluru, June-Hong Park, Jungyu Lee, Ji-Hoon Lim
  • Publication number: 20200365215
    Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Inventors: Young-sun MIN, Vivek Venkata KALLURU, Tae-hong KWON, Ki-won KIM, Sung-whan SEO, Bilal Ahmad JANJUA
  • Patent number: 10818352
    Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and plurality of bit lines to corresponding rows and columns of the resistive memory cells. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance, which is greater than the first parasitic resistance.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-gyu Lee, Yong-jun Lee, Bilal Ahmad Janjua, Chea-ouk Lim, Makoto Hirano
  • Patent number: 10707751
    Abstract: An electronic circuit includes a first switch circuit, a second switch circuit, a pumping circuit, and a main charge pump. The first switch circuit transfers a first driving voltage to a first node based on a first clock. The second switch circuit transfers a second driving voltage to a second node based on the first driving voltage of the first node. The pumping circuit outputs a pumping voltage having a level corresponding to a sum of a level of the second driving voltage and a first operation level of a second clock, based on the second driving voltage of the second node and the first operation level. The main charge pump converts an input voltage based on the pumping voltage.
    Type: Grant
    Filed: August 24, 2019
    Date of Patent: July 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bilal Ahmad Janjua, Sungwhan Seo, Vivek Venkata Kalluru
  • Patent number: 10685707
    Abstract: A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, each of the plurality of memory cells including a switching element and an information storage element connected to the switching element and containing a phase-change material, a decoder unit configured to determine a selected word line and a selected bit line connected to a selected memory cell to read data, among the plurality of memory cells, and a current compensation circuit configured to remove a leakage current from the selected word line, the leakage current corresponding to a sun of off-currents flowing in unselected bit lines, excluding the selected bit line, among the plurality of bit lines, from the selected word line.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Venkataramana Gangasani, Tae Hui Na, Bilal Ahmad Janjua
  • Publication number: 20200152277
    Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 14, 2020
    Inventors: Young-sun MIN, Vivek Venkata KALLURU, Tae-hong KWON, Ki-won KIM, Sung-whan SEO, Bilal Ahmad JANJUA
  • Publication number: 20200152265
    Abstract: A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.
    Type: Application
    Filed: August 17, 2019
    Publication date: May 14, 2020
    Inventors: BILAL AHMAD JANJUA, VIVEK VENKATA KALLURU, JUNE-HONG PARK, JUNGYU LEE, JI-HOON LIM
  • Publication number: 20200144910
    Abstract: An electronic circuit includes a first switch circuit, a second switch circuit, a pumping circuit, and a main charge pump. The first switch circuit transfers a first driving voltage to a first node based on a first clock. The second switch circuit transfers a second driving voltage to a second node based on the first driving voltage of the first node. The pumping circuit outputs a pumping voltage having a level corresponding to a sum of a level of the second driving voltage and a first operation level of a second clock, based on the second driving voltage of the second node and the first operation level. The main charge pump converts an input voltage based on the pumping voltage.
    Type: Application
    Filed: August 24, 2019
    Publication date: May 7, 2020
    Inventors: BILAL AHMAD JANJUA, SUNGWHAN SEO, VIVEK VENKATA KALLURU
  • Publication number: 20200105345
    Abstract: A leakage current compensation device includes a current supply unit configured to supply a current to at least one operating cell, among a plurality of cells of a memory device disposed at intersections of wordlines and bitlines, a leakage current sensing unit configured to sense an amount of leakage current flowing to a non-operating cell among the cells to output a result value based on the sensed amount of leakage current, and a compensation current supply unit configured to receive the result value and supply a compensation current to the operating cell.
    Type: Application
    Filed: April 15, 2019
    Publication date: April 2, 2020
    Inventors: JONG MIN BAEK, VIVEK VENKATA KALLURU, JONG RYUL KIM, BILAL AHMAD JANJUA
  • Publication number: 20200098427
    Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and a plurality bit lines to corresponding rows and columns of resistive memory cells in the array. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance associated therewith is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance associated therewith, which is greater than the first parasitic resistance.
    Type: Application
    Filed: May 16, 2019
    Publication date: March 26, 2020
    Inventors: Jun-gyu Lee, Yong-jun Lee, Bilal Ahmad Janjua, Chea-ouk Lim, Makoto Hirano
  • Publication number: 20200090745
    Abstract: A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, each of the plurality of memory cells including a switching element and an information storage element connected to the switching element and containing a phase-change material, a decoder unit configured to determine a selected word line and a selected bit line connected to a selected memory cell to read data, among the plurality of memory cells, and a current compensation circuit configured to remove a leakage current from the selected word line, the leakage current corresponding to a sun of off-currents flowing in unselected bit lines, excluding the selected bit line, among the plurality of bit lines, from the selected word line.
    Type: Application
    Filed: April 9, 2019
    Publication date: March 19, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Venkataramana GANGASANI, Tae Hui NA, Bilal Ahmad JANJUA
  • Patent number: 9147489
    Abstract: A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a PMOS transistor configured to transfer the second driving voltage provided to a first terminal of the PMOS transistor from the depletion type NMOS transistor to a second terminal of the PMOS transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the PMOS transistor.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: September 29, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taehyun Kim, Youngsun Min, Bilal Ahmad Janjua, Jeongdon Ihm
  • Publication number: 20140204676
    Abstract: A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a PMOS transistor configured to transfer the second driving voltage provided to a first terminal of the PMOS transistor from the depletion type NMOS transistor to a second terminal of the PMOS transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the PMOS transistor.
    Type: Application
    Filed: November 12, 2013
    Publication date: July 24, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taehyun Kim, Youngsun Min, Bilal Ahmad Janjua, Jeongdon Ihm