Abstract: A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and plurality of bit lines to corresponding rows and columns of the resistive memory cells. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance, which is greater than the first parasitic resistance.

Abstract: An electronic circuit includes a first switch circuit, a second switch circuit, a pumping circuit, and a main charge pump. The first switch circuit transfers a first driving voltage to a first node based on a first clock. The second switch circuit transfers a second driving voltage to a second node based on the first driving voltage of the first node. The pumping circuit outputs a pumping voltage having a level corresponding to a sum of a level of the second driving voltage and a first operation level of a second clock, based on the second driving voltage of the second node and the first operation level. The main charge pump converts an input voltage based on the pumping voltage.

Abstract: A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, each of the plurality of memory cells including a switching element and an information storage element connected to the switching element and containing a phase-change material, a decoder unit configured to determine a selected word line and a selected bit line connected to a selected memory cell to read data, among the plurality of memory cells, and a current compensation circuit configured to remove a leakage current from the selected word line, the leakage current corresponding to a sun of off-currents flowing in unselected bit lines, excluding the selected bit line, among the plurality of bit lines, from the selected word line.

Abstract: A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Abstract: An electronic circuit includes a first switch circuit, a second switch circuit, a pumping circuit, and a main charge pump. The first switch circuit transfers a first driving voltage to a first node based on a first clock. The second switch circuit transfers a second driving voltage to a second node based on the first driving voltage of the first node. The pumping circuit outputs a pumping voltage having a level corresponding to a sum of a level of the second driving voltage and a first operation level of a second clock, based on the second driving voltage of the second node and the first operation level. The main charge pump converts an input voltage based on the pumping voltage.

Abstract: Methods and apparatus provide flexible allocation and regulation of scheduled energy transfers between energy storage devices (“batteries”) and a power grid. Piecewise mappings having at least one sloping segment enable gradual variations in scheduled energy transfers as cleared values of a medium of energy exchange deviate from predicted values of the medium of energy exchange. Thereby deviations from a battery's predicted energy transfer schedule can be reduced, and overall smoother operation of a power grid can be achieved. Two sloping linear segments can be separated by a dead band, a portion of the mapping in which the scheduled energy transfer amount is invariant. A dead zone can increase the likelihood of a battery meeting its predicted schedule.

Abstract: A leakage current compensation device includes a current supply unit configured to supply a current to at least one operating cell, among a plurality of cells of a memory device disposed at intersections of wordlines and bitlines, a leakage current sensing unit configured to sense an amount of leakage current flowing to a non-operating cell among the cells to output a result value based on the sensed amount of leakage current, and a compensation current supply unit configured to receive the result value and supply a compensation current to the operating cell.

Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and a plurality bit lines to corresponding rows and columns of resistive memory cells in the array. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance associated therewith is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance associated therewith, which is greater than the first parasitic resistance.

Abstract: A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, each of the plurality of memory cells including a switching element and an information storage element connected to the switching element and containing a phase-change material, a decoder unit configured to determine a selected word line and a selected bit line connected to a selected memory cell to read data, among the plurality of memory cells, and a current compensation circuit configured to remove a leakage current from the selected word line, the leakage current corresponding to a sun of off-currents flowing in unselected bit lines, excluding the selected bit line, among the plurality of bit lines, from the selected word line.

Abstract: A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a PMOS transistor configured to transfer the second driving voltage provided to a first terminal of the PMOS transistor from the depletion type NMOS transistor to a second terminal of the PMOS transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the PMOS transistor.

Abstract: A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a PMOS transistor configured to transfer the second driving voltage provided to a first terminal of the PMOS transistor from the depletion type NMOS transistor to a second terminal of the PMOS transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the PMOS transistor.

Abstract: High-speed communication links are improved by having differential pairs of traces in a connector pinfield on layers of a multilayer printed circuit board (PCB) to straddle respective rows of reference (ground) pins rather than the respective rows of signal vias. Thus, a desirable increase in the size of each an anti-pad to surrounding each signal via pad can be incorporated without forcing tracing of adjacent differential pairs closer to one another, and thus increased cross talk is avoided. Thereby, 50 ohm or close to 50 ohm impedance for each signal via is achieved. Spacing and routing between traces of each differential pair are advantageously adjusted for skew compensation and impedance optimization utilizing three dimensional computational electromagnetic tools.

Abstract: High-speed communication links are improved by having differential pairs of traces in a connector pinfield on layers of a multilayer printed circuit board (PCB) to straddle respective rows of reference (ground) pins rather than the respective rows of signal vias. Thus, a desirable increase in the size of each an anti-pad to surrounding each signal via pad can be incorporated without forcing tracing of adjacent differential pairs closer to one another, and thus increased cross talk is avoided. Thereby, 50 ohm or close to 50 ohm impedance for each signal via is achieved. Spacing and routing between traces of each differential pair are advantageously adjusted for skew compensation and impedance optimization utilizing three dimensional computational electromagnetic tools.

Abstract: A circuit board includes a pair of interconnects configured to support conveyance of a differential mode communication signal, which comprises a balanced first signal (e.g., signal X) and corresponding second signal (e.g., signal ?X) of opposite polarities. A transmitter circuit coupled to the pair of interconnects supports generation of a non-differential mode communication signal that is different than a classic differential mode communication signal. A receiver circuit coupled to the first pair of interconnects supports reception of the non-differential mode communication signal. Thus, the pair of interconnects convey the non-differential mode communication signal instead of the differential mode communication signal, mitigating interference with other pairs of interconnects on the circuit board that convey yet other communication signals.

Abstract: A method and system that communicates adaptive transmit-side filter updates between a receiver and transmitter inserts additional versions of control codes into a back channel for encoding updates. Since the control codes are required in the back channel, no additional bandwidth of the back channel is used to communicate the updates.

Abstract: A circuit board has, in a first signal layer, a signal conductor having a relatively small width and a contact pad having a relatively large width. The relatively large width of the contact pad combined with the relatively narrow signal conductor creates an impedance mismatch between the contact pad and the signal conductor. The circuit board has, in a second signal layer, a ground plane separated from the first signal layer by a nonconductive layer. The circuit board defines an opening in the second signal layer underneath the contact pad. The presence of the ground plane underneath the contact pad typically affects the impedance of the contact pad. The opening in the second signal layer removes a portion the ground plane relative to the contact pad and, therefore, reduces the impedance mismatch between the contact pad and the signal conductor.

Abstract: A modified connector footprint on a PWB includes a row of ground vias disposed outside a standard connector footprint that do not mate to pins in the connector. The extra ground vias provide additional shielding and reduce cross-talk in the connector/PWB interface.