Abstract: A system and method estimate the fault severity index and consequently the number of shorted turns in permanent magnet motors (PMSM) with inter turn short circuit fault (ITSC). In this method, the machine is excited with DC current at stand still conditions to obtain the winding resistance seen by the d-axis of the machine. The estimated d-axis resistance contains useful information pertaining to the fault severity index, and is used to extract the fault severity index and the number of shorted turns in the faulty motor. The method enables the estimation of fault severity index without complex modeling with different machine prototypes, or FEA models to analyze the relationship between machine currents and short circuit current. To enhance the accuracy of the estimation method, this disclosure addresses issues associated with inverter non-linearity effects such as distortion voltage due to dead time effects and voltage drops across the switching devices.

Abstract: A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channel

Abstract: A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channel

Abstract: A method of measuring a junction temperature of a SiC MOSFET can be provided by applying a gate-source voltage to an external gate loop coupled to a gate of the SiC MOSFET, detecting a first time when the gate-source voltage exceeds a first value configured to disable conduction of a current in a drain of the SiC MOSFET, detecting, after the first time, a second time when a voltage across a common source inductance in a package of the SiC MOSFET indicates that the current in the drain is greater than a reference value, defining a time interval from the first time to the second time as a turn on delay time of the SiC MOSFET and determining the junction temperature for the SiC MOSFET using the turn on delay time.

Abstract: Embodiments according to the invention can provide methods of testing a SiC MOSFET, that can include applying first and second voltage levels across a gate-source junction of a SiC MOSFET and measuring first and second voltage drops across a reverse body diode included in the SiC MOSFET responsive to the first and second voltage levels, respectively, to provide an indication of a degradation of a gate oxide of the SiC MOSFET and an indication of contact resistance of the SiC MOSFET, respectively.

Abstract: A method of monitoring a condition of a SiC MOSFET can include (a) applying a first test gate-source voltage across a gate-source of a SiC MOSFET in-situ, the first test gate-source voltage configured to operate the SiC MOSFET in saturation mode to generate a first drain current in the SiC MOSFET, (b) applying a second test gate-source voltage across the gate-source of the SiC MOSFET in-situ, the second test gate-source voltage configured to operate the SiC MOSFET in fully-on mode to generate a second drain current in the SiC MOSFET, (c) determining a drain-source saturation resistance using the first drain current to provide an indication of a degradation of a gate oxide of the SiC MOSFET; and (d) determining a drain-source on resistance using the second drain current to provide an indication of a degradation of contact resistance of the SiC MOSFET.

Abstract: A system and method estimate the fault severity index and consequently the number of shorted turns in permanent magnet motors (PMSM) with inter turn short circuit fault (ITSC). In this method, the machine is excited with DC current at stand still conditions to obtain the winding resistance seen by the d-axis of the machine. The estimated d-axis resistance contains useful information pertaining to the fault severity index, and is used to extract the fault severity index and the number of shorted turns in the faulty motor. The method enables the estimation of fault severity index without complex modeling with different machine prototypes, or FEA models to analyze the relationship between machine currents and short circuit current. To enhance the accuracy of the estimation method, this disclosure addresses issues associated with inverter non-linearity effects such as distortion voltage due to dead time effects and voltage drops across the switching devices.

Abstract: A method of measuring a junction temperature of a SiC MOSFET can be provided by applying a gate-source voltage to an external gate loop coupled to a gate of the SiC MOSFET, detecting a first time when the gate-source voltage exceeds a first value configured to disable conduction of a current in a drain of the SiC MOSFET, detecting, after the first time, a second time when a voltage across a common source inductance in a package of the SiC MOSFET indicates that the current in the drain is greater than a reference value, defining a time interval from the first time to the second time as a turn on delay time of the SiC MOSFET and determining the junction temperature for the SiC MOSFET using the turn on delay time.

Abstract: Embodiments according to the invention can provide methods of testing a SiC MOSFET, that can include applying first and second voltage levels across a gate-source junction of a SiC MOSFET and measuring first and second voltage drops across a reverse body diode included in the SiC MOSFET responsive to the first and second voltage levels, respectively, to provide an indication of a degradation of a gate oxide of the SiC MOSFET and an indication of contact resistance of the SiC MOSFET, respectively.

Abstract: A method of monitoring a condition of a SiC MOSFET can include (a) applying a first test gate-source voltage across a gate-source of a SiC MOSFET in-situ, the first test gate-source voltage configured to operate the SiC MOSFET in saturation mode to generate a first drain current in the SiC MOSFET, (b) applying a second test gate-source voltage across the gate-source of the SiC MOSFET in-situ, the second test gate-source voltage configured to operate the SiC MOSFET in fully-on mode to generate a second drain current in the SiC MOSFET, (c) determining a drain-source saturation resistance using the first drain current to provide an indication of a degradation of a gate oxide of the SiC MOSFET; and (d) determining a drain-source on resistance using the second drain current to provide an indication of a degradation of contact resistance of the SiC MOSFET.

Abstract: A method of controlling a plurality of permanent magnet synchronous motors using a single inverter that includes obtaining an estimate of rotor position and speed individually for a plurality of permanent magnet synchronous motors. The method can include calculating the average rotor position from the obtained estimate of the rotor position for each permanent magnet synchronous motor of the plurality of permanent magnet synchronous motors. The method can include reconstructing a rotor permanent-magnet flux for each permanent magnet synchronous motor and transforming the reconstructed rotor permanent-magnet flux for each permanent magnet synchronous motor to average fluxes and average differential fluxes on an average d-q reference frame. The method can include obtaining the average current reference in the average d-q reference frame for the plurality of permanent magnet synchronous motors; and determining an inverter voltage reference.

Abstract: A method of controlling a plurality of permanent magnet synchronous motors using a single inverter that includes obtaining an estimate of rotor position and speed individually for a plurality of permanent magnet synchronous motors. The method can include calculating the average rotor position from the obtained estimate of the rotor position for each permanent magnet synchronous motor of the plurality of permanent magnet synchronous motors. The method can include reconstructing a rotor permanent-magnet flux for each permanent magnet synchronous motor and transforming the reconstructed rotor permanent-magnet flux for each permanent magnet synchronous motor to average fluxes and average differential fluxes on an average d-q reference frame. The method can include obtaining the average current reference in the average d-q reference frame for the plurality of permanent magnet synchronous motors; and determining an inverter voltage reference.

Abstract: A method for driving a motor having a plurality of phases is provided. Initially, first, second, and third intervals for a pulse width modulation (PWM) period from first and second voltage commands are generated. The first and second voltage commands correspond to a voltage vector for the motor, and the voltage vector has an associated sector. A conversion formula is then determined for the first, second, third intervals based on the associated sector for the voltage vector. Using the conversion formula and the first, second, and third intervals, fourth, fifth, and sixth intervals are generated, and a set of PWM signals for the PWM period is generated from the fourth, fifth, and sixth intervals. The motor is then driven with the second set of PWM signals, and a current traversing the plurality of phases with a single shunt is measured.

Abstract: A method for driving a motor having a plurality of phases is provided. Initially, first, second, and third intervals for a pulse width modulation (PWM) period from first and second voltage commands are generated. The first and second voltage commands correspond to a voltage vector for the motor, and the voltage vector has an associated sector. A conversion formula is then determined for the first, second, third intervals based on the associated sector for the voltage vector. Using the conversion formula and the first, second, and third intervals, fourth, fifth, and sixth intervals are generated, and a set of PWM signals for the PWM period is generated from the fourth, fifth, and sixth intervals. The motor is then driven with the second set of PWM signals, and a current traversing the plurality of phases with a single shunt is measured.