Patents by Inventor Bilal Akin
Bilal Akin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12584799Abstract: An apparatus and method are provided for estimating junction temperature in a metal-oxide-semiconductor field-effect transistor (MOSFET), such as a silicon carbide (SiC) MOSFET, by capturing switching transients in a source path. A measurement circuit detects a voltage across a stray inductive element during a turn-on or turn-off phase and converts the transient into a pulse having a width proportional to a rise time or fall time. A processor determines junction temperature based on the pulse width and stored correlations between transient durations and temperature. An auxiliary switch circuit may temporarily insert a gate resistance to facilitate transient capture. Aging effects are compensated by analyzing temperature-dependent variations in rise and fall times to adjust temperature estimation over the device lifetime. The system can be integrated into gate driver circuitry for real-time monitoring without substantial disruption to normal converter operation.Type: GrantFiled: October 30, 2023Date of Patent: March 24, 2026Assignee: Board of Regents, The University of Texas SystemInventors: Bilal Akin, Masoud Farhadi, Abdolrahman Sajadi, Bhanu Teja Vankayalapati
-
Publication number: 20260029306Abstract: Disclosed herein are techniques for detecting faults in motor bearings. The techniques can include obtaining operational data indicative of the motor's electromotive functionality and analyzing this data to extract performance metrics. Fault conditions can be determined by comparing these metrics with baseline values from normal motor operation. Alerts can be generated when deviations exceed predefined thresholds. The techniques can dynamically determine thresholds based on short-term and long-term statistical variances from baseline metrics, reflecting early-stage anomalies and advanced faults. Performance metrics can include root mean square (RMS) values, peak values, and crest factors. The techniques can support trend analysis to predict maintenance needs and can utilize lightweight algorithms for real-time monitoring on low-end controllers. Notifications of fault conditions can be transmitted to remote monitoring systems.Type: ApplicationFiled: July 23, 2024Publication date: January 29, 2026Inventors: Bilal Akin, Mojtaba Afshar, Chen Li
-
Publication number: 20250102369Abstract: The inventive concepts disclosed herein can relate to assessment of junction temperature (Tj) in metal-oxide-semiconductor field-effect transistors (MOSFETs), such as silicon carbide (SiC) MOSFETS. Voltage transients, characterized by rise time and/or fall time, can be captured in the common source stray inductance during the MOSFET's turn-on and turn-off phases. The captured voltage transients can be transformed into signals having pulse widths that correspond to the duration of the rise time or fall time. These pulse widths can serve as a data source for determining junction temperature and/or for accounting for the effects of device aging.Type: ApplicationFiled: October 30, 2023Publication date: March 27, 2025Inventors: Bilal Akin, Masoud Farhadi, Abdolrahman Sajadi, Bhanu Teja Vankayalapati
-
Patent number: 11843339Abstract: A system and method estimate the fault severity index and consequently the number of shorted turns in permanent magnet motors (PMSM) with inter turn short circuit fault (ITSC). In this method, the machine is excited with DC current at stand still conditions to obtain the winding resistance seen by the d-axis of the machine. The estimated d-axis resistance contains useful information pertaining to the fault severity index, and is used to extract the fault severity index and the number of shorted turns in the faulty motor. The method enables the estimation of fault severity index without complex modeling with different machine prototypes, or FEA models to analyze the relationship between machine currents and short circuit current. To enhance the accuracy of the estimation method, this disclosure addresses issues associated with inverter non-linearity effects such as distortion voltage due to dead time effects and voltage drops across the switching devices.Type: GrantFiled: January 20, 2021Date of Patent: December 12, 2023Assignee: Board of Regents, The University of Texas SystemInventors: Bilal Akin, Kudra Baruti, Vigneshwaran Gurusamy, Feyzullah Erturk
-
Publication number: 20230076735Abstract: A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channelType: ApplicationFiled: September 9, 2021Publication date: March 9, 2023Inventors: Bhanu Teja Vankayalapati, Bilal Akin, Shi Pu, Fei Yang, Masoud Farhadi
-
Patent number: 11585844Abstract: A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channelType: GrantFiled: September 9, 2021Date of Patent: February 21, 2023Assignee: Board of Regents, The University of Texas SystemInventors: Bhanu Teja Vankayalapati, Bilal Akin, Shi Pu, Fei Yang, Masoud Farhadi
-
Patent number: 11525740Abstract: A method of measuring a junction temperature of a SiC MOSFET can be provided by applying a gate-source voltage to an external gate loop coupled to a gate of the SiC MOSFET, detecting a first time when the gate-source voltage exceeds a first value configured to disable conduction of a current in a drain of the SiC MOSFET, detecting, after the first time, a second time when a voltage across a common source inductance in a package of the SiC MOSFET indicates that the current in the drain is greater than a reference value, defining a time interval from the first time to the second time as a turn on delay time of the SiC MOSFET and determining the junction temperature for the SiC MOSFET using the turn on delay time.Type: GrantFiled: June 23, 2020Date of Patent: December 13, 2022Assignee: Boards of Regents, The University of Texas SystemInventors: Bilal Akin, Fei Yang, Shi Pu, Chi Xu, Bhanu Vankayalapati
-
Patent number: 11474145Abstract: Embodiments according to the invention can provide methods of testing a SiC MOSFET, that can include applying first and second voltage levels across a gate-source junction of a SiC MOSFET and measuring first and second voltage drops across a reverse body diode included in the SiC MOSFET responsive to the first and second voltage levels, respectively, to provide an indication of a degradation of a gate oxide of the SiC MOSFET and an indication of contact resistance of the SiC MOSFET, respectively.Type: GrantFiled: June 10, 2020Date of Patent: October 18, 2022Assignee: Board of Regents, The University of Texas SystemInventors: Enes Ugur, Bilal Akin, Fei Yang, Shi Pu, Chi Xu
-
Patent number: 11397209Abstract: A method of monitoring a condition of a SiC MOSFET can include (a) applying a first test gate-source voltage across a gate-source of a SiC MOSFET in-situ, the first test gate-source voltage configured to operate the SiC MOSFET in saturation mode to generate a first drain current in the SiC MOSFET, (b) applying a second test gate-source voltage across the gate-source of the SiC MOSFET in-situ, the second test gate-source voltage configured to operate the SiC MOSFET in fully-on mode to generate a second drain current in the SiC MOSFET, (c) determining a drain-source saturation resistance using the first drain current to provide an indication of a degradation of a gate oxide of the SiC MOSFET; and (d) determining a drain-source on resistance using the second drain current to provide an indication of a degradation of contact resistance of the SiC MOSFET.Type: GrantFiled: June 10, 2020Date of Patent: July 26, 2022Assignee: Board of Regents, The University of Texas SystemInventors: Bilal Akin, Shi Pu, Enes Ugur, Fei Yang, Chi Xu, Bhanu Teja Vankayalapati
-
Publication number: 20220231629Abstract: A system and method estimate the fault severity index and consequently the number of shorted turns in permanent magnet motors (PMSM) with inter turn short circuit fault (ITSC). In this method, the machine is excited with DC current at stand still conditions to obtain the winding resistance seen by the d-axis of the machine. The estimated d-axis resistance contains useful information pertaining to the fault severity index, and is used to extract the fault severity index and the number of shorted turns in the faulty motor. The method enables the estimation of fault severity index without complex modeling with different machine prototypes, or FEA models to analyze the relationship between machine currents and short circuit current. To enhance the accuracy of the estimation method, this disclosure addresses issues associated with inverter non-linearity effects such as distortion voltage due to dead time effects and voltage drops across the switching devices.Type: ApplicationFiled: January 20, 2021Publication date: July 21, 2022Applicant: Board of Regents, The University of Texas SystemInventors: Bilal Akin, Kudra Baruti, Vigneshwaran Gurusamy, Feyzullah Erturk
-
Publication number: 20210396596Abstract: A method of measuring a junction temperature of a SiC MOSFET can be provided by applying a gate-source voltage to an external gate loop coupled to a gate of the SiC MOSFET, detecting a first time when the gate-source voltage exceeds a first value configured to disable conduction of a current in a drain of the SiC MOSFET, detecting, after the first time, a second time when a voltage across a common source inductance in a package of the SiC MOSFET indicates that the current in the drain is greater than a reference value, defining a time interval from the first time to the second time as a turn on delay time of the SiC MOSFET and determining the junction temperature for the SiC MOSFET using the turn on delay time.Type: ApplicationFiled: June 23, 2020Publication date: December 23, 2021Inventors: Bilal Akin, Fei Yang, Shi Pu, Chi Xu, Bhanu Vankayalapati
-
Publication number: 20200408829Abstract: Embodiments according to the invention can provide methods of testing a SiC MOSFET, that can include applying first and second voltage levels across a gate-source junction of a SiC MOSFET and measuring first and second voltage drops across a reverse body diode included in the SiC MOSFET responsive to the first and second voltage levels, respectively, to provide an indication of a degradation of a gate oxide of the SiC MOSFET and an indication of contact resistance of the SiC MOSFET, respectively.Type: ApplicationFiled: June 10, 2020Publication date: December 31, 2020Inventors: Enes Ugur, Bilal Akin, Fei Yang, Shi Pu, Chi Xu
-
Publication number: 20200400738Abstract: A method of monitoring a condition of a SiC MOSFET can include (a) applying a first test gate-source voltage across a gate-source of a SiC MOSFET in-situ, the first test gate-source voltage configured to operate the SiC MOSFET in saturation mode to generate a first drain current in the SiC MOSFET, (b) applying a second test gate-source voltage across the gate-source of the SiC MOSFET in-situ, the second test gate-source voltage configured to operate the SiC MOSFET in fully-on mode to generate a second drain current in the SiC MOSFET, (c) determining a drain-source saturation resistance using the first drain current to provide an indication of a degradation of a gate oxide of the SiC MOSFET; and (d) determining a drain-source on resistance using the second drain current to provide an indication of a degradation of contact resistance of the SiC MOSFET.Type: ApplicationFiled: June 10, 2020Publication date: December 24, 2020Inventors: Bilal Akin, Shi Pu, Enes Ugur, Fei Yang, Chi Xu, Bhanu Teja Vankayalapati
-
Patent number: 10389286Abstract: A method of controlling a plurality of permanent magnet synchronous motors using a single inverter that includes obtaining an estimate of rotor position and speed individually for a plurality of permanent magnet synchronous motors. The method can include calculating the average rotor position from the obtained estimate of the rotor position for each permanent magnet synchronous motor of the plurality of permanent magnet synchronous motors. The method can include reconstructing a rotor permanent-magnet flux for each permanent magnet synchronous motor and transforming the reconstructed rotor permanent-magnet flux for each permanent magnet synchronous motor to average fluxes and average differential fluxes on an average d-q reference frame. The method can include obtaining the average current reference in the average d-q reference frame for the plurality of permanent magnet synchronous motors; and determining an inverter voltage reference.Type: GrantFiled: March 7, 2016Date of Patent: August 20, 2019Assignees: SCHLUMBERGER TECHNOLOGY CORPORATION, BOARD OF REGENTS/THE UNIVERSITY OF TEXAS SYSTEMInventors: Zhuangyao Tang, Bilal Akin, Xuedong Yang, Maxim Klyuzhev
-
Publication number: 20170257048Abstract: A method of controlling a plurality of permanent magnet synchronous motors using a single inverter that includes obtaining an estimate of rotor position and speed individually for a plurality of permanent magnet synchronous motors. The method can include calculating the average rotor position from the obtained estimate of the rotor position for each permanent magnet synchronous motor of the plurality of permanent magnet synchronous motors. The method can include reconstructing a rotor permanent-magnet flux for each permanent magnet synchronous motor and transforming the reconstructed rotor permanent-magnet flux for each permanent magnet synchronous motor to average fluxes and average differential fluxes on an average d-q reference frame. The method can include obtaining the average current reference in the average d-q reference frame for the plurality of permanent magnet synchronous motors; and determining an inverter voltage reference.Type: ApplicationFiled: March 7, 2016Publication date: September 7, 2017Inventors: Zhuangyao Tang, Bilal Akin, Xuedong Yang, Maxim Klyuzhev
-
Patent number: 8907611Abstract: A method for driving a motor having a plurality of phases is provided. Initially, first, second, and third intervals for a pulse width modulation (PWM) period from first and second voltage commands are generated. The first and second voltage commands correspond to a voltage vector for the motor, and the voltage vector has an associated sector. A conversion formula is then determined for the first, second, third intervals based on the associated sector for the voltage vector. Using the conversion formula and the first, second, and third intervals, fourth, fifth, and sixth intervals are generated, and a set of PWM signals for the PWM period is generated from the fourth, fifth, and sixth intervals. The motor is then driven with the second set of PWM signals, and a current traversing the plurality of phases with a single shunt is measured.Type: GrantFiled: July 14, 2011Date of Patent: December 9, 2014Assignee: Texas Instruments IncorporatedInventors: Ling Qin, Bilal Akin
-
Publication number: 20130015793Abstract: A method for driving a motor having a plurality of phases is provided. Initially, first, second, and third intervals for a pulse width modulation (PWM) period from first and second voltage commands are generated. The first and second voltage commands correspond to a voltage vector for the motor, and the voltage vector has an associated sector. A conversion formula is then determined for the first, second, third intervals based on the associated sector for the voltage vector. Using the conversion formula and the first, second, and third intervals, fourth, fifth, and sixth intervals are generated, and a set of PWM signals for the PWM period is generated from the fourth, fifth, and sixth intervals. The motor is then driven with the second set of PWM signals, and a current traversing the plurality of phases with a single shunt is measured.Type: ApplicationFiled: July 14, 2011Publication date: January 17, 2013Applicant: Texas Instruments IncorporatedInventors: Ling Qin, Bilal Akin