Patents by Inventor Bilal Khalaf
Bilal Khalaf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11894334Abstract: Embodiments disclosed herein include wire bonds and tools for forming wire bonds. In an embodiment, a wire bond may comprise a first attachment ball, and a first wire having a first portion contacting the first attachment ball and a second portion. In an embodiment, the wire bond may further comprise a second attachment ball, and a second wire having a first portion contacting the second attachment ball and a second portion. In an embodiment, the second portion of the first wire is connected to the second portion of the second wire.Type: GrantFiled: October 15, 2018Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Yuhong Cai, Bilal Khalaf, Yi Xu
-
Patent number: 11848311Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.Type: GrantFiled: February 25, 2022Date of Patent: December 19, 2023Assignee: Intel CorporationInventor: Bilal Khalaf
-
Patent number: 11817438Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.Type: GrantFiled: January 14, 2019Date of Patent: November 14, 2023Assignee: Intel CorporationdInventors: Hyoung Il Kim, Bilal Khalaf, Juan E. Dominguez, John G. Meyers
-
Patent number: 11811182Abstract: Embodiments disclosed herein include electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first substrate and a plurality of first conductive pads on the first substrate. In an embodiment, the electronics package further comprises a second substrate and a plurality of second conductive pads on the second substrate. In an embodiment, the electronics package further comprises a plurality of interconnects between the first and second substrate. In an embodiment, each interconnect electrically couples one of the first conductive pads to one of the second conductive pads. In an embodiment, the interconnects comprise strands of conductive material that are woven on themselves to form a mesh-like structure.Type: GrantFiled: October 11, 2018Date of Patent: November 7, 2023Assignee: Intel CorporationInventors: Tyler Leuten, Mohammed Rahman, Bilal Khalaf
-
Patent number: 11710674Abstract: Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.Type: GrantFiled: March 29, 2022Date of Patent: July 25, 2023Assignee: Intel CorporationInventors: Yi Elyn Xu, Bilal Khalaf, Dennis Sean Carr
-
Patent number: 11700696Abstract: Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.Type: GrantFiled: June 3, 2021Date of Patent: July 11, 2023Assignee: Intel CorporationInventors: Florence R. Neumann, Bilal Khalaf, Saeed S. Shojaie
-
Publication number: 20220223487Abstract: Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Inventors: Yi Elyn Xu, Bilal Khalaf, Dennis Sean Carr
-
Patent number: 11373974Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having a bond finger, a die coupled to the substrate and having a bond pad, a first bond wire coupled between the bond pad and the bond finger, and a second bond wire coupled between the bond pad and the bond finger. The first bond wire is reverse bonded between a pad solder ball on the bond pad and a finger solder ball on the bond finger. The second bond wire is forward bonded between a supplemental pad solder ball on the pad solder and the bond finger adjacent the finger solder ball. Associated systems and methods are also disclosed.Type: GrantFiled: July 1, 2016Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Bilal Khalaf, Mao Guo
-
Publication number: 20220181306Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.Type: ApplicationFiled: February 25, 2022Publication date: June 9, 2022Applicant: Intel CorporationInventor: Bilal Khalaf
-
Patent number: 11329027Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.Type: GrantFiled: April 26, 2016Date of Patent: May 10, 2022Assignee: Intel CorporationInventor: Bilal Khalaf
-
Patent number: 11315843Abstract: Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.Type: GrantFiled: December 28, 2016Date of Patent: April 26, 2022Assignee: Intel CorporationInventors: Yi Elyn Xu, Bilal Khalaf, Dennis Sean Carr
-
Patent number: 11145632Abstract: A high density die package configuration is shown for use on system boards. In one example, an apparatus includes a system board, a first package mounted to the system board, a second package mounted to the system board, and an interface package mounted between the first and the second package and coupled directly to the first package and to the second package through the respective first and second packages.Type: GrantFiled: September 29, 2017Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Juan E. Dominguez, Hyoung Il Kim, Bilal Khalaf, John Gary Meyers
-
Publication number: 20210298183Abstract: Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.Type: ApplicationFiled: June 3, 2021Publication date: September 23, 2021Inventors: Florence R. PON, Bilal KHALAF, Saeed S. SHOJAIE
-
Patent number: 11064612Abstract: Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.Type: GrantFiled: April 1, 2016Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Florence R. Pon, Bilal Khalaf, Saeed S. Shojaie
-
Publication number: 20210202442Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.Type: ApplicationFiled: April 26, 2016Publication date: July 1, 2021Applicant: Intel CorporationInventor: Bilal Khalaf
-
Publication number: 20210074668Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having a bond finger, a die coupled to the substrate and having a bond pad, a first bond wire coupled between the bond pad and the bond finger, and a second bond wire coupled between the bond pad and the bond finger. The first bond wire is reverse bonded between a pad solder ball on the bond pad and a finger solder ball on the bond finger. The second bond wire is forward bonded between a supplemental pad solder ball on the pad solder and the bond finger adjacent the finger solder ball. Associated systems and methods are also disclosed.Type: ApplicationFiled: July 1, 2016Publication date: March 11, 2021Applicant: Intel CorporationInventors: Bilal Khalaf, Mao Guo
-
Patent number: 10879152Abstract: An apparatus is provided which comprises: a substrate; a stacked ring structure disposed on the substrate, the stacked ring structure comprising a first ring and a second ring; a first partial through-mold-via (TMV) formed on the first ring; and a second partial TMV formed on the second ring, wherein the first ring and the second ring are stacked such that the first partial TMV is aligned on top of the second partial TMV.Type: GrantFiled: December 14, 2016Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: Yi Elyn Xu, Bilal Khalaf
-
Publication number: 20200381406Abstract: A high density die package configuration is shown for use on system boards. In one example, an apparatus includes a system board, a first package mounted to the system board, a second package mounted to the system board, and an interface package mounted between the first and the second package and coupled directly to the first package and to the second package through the respective first and second packages.Type: ApplicationFiled: September 29, 2017Publication date: December 3, 2020Inventors: Juan E. DOMINGUEZ, Hyoung Il KIM, Bilal KHALAF, John Gary MEYERS
-
Patent number: 10847450Abstract: A bond-wire system including a wire bond that is deflected above a dielectric ridge at a die edge. The deflected wire bond allows for both a lowered Z-profile and a reduced X-Y footprint. The bond-wire system may include a stacked-die configuration where a stacked die is wire bonded and the stacked-die bond wire is deflected above a dielectric ridge at the stacked die edge.Type: GrantFiled: September 28, 2016Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Saeed Shojaie, Hyoung Il Kim, Bilal Khalaf, Min-Tih Ted Lai
-
Publication number: 20200227393Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.Type: ApplicationFiled: January 14, 2019Publication date: July 16, 2020Inventors: Hyoung Il KIM, Bilal KHALAF, Juan E. DOMINGUEZ, John G. MEYERS