Abstract: The present disclosure detects and/or prevents power analysis side-channel attacks without requiring the use of external measurement devices. A first portion of field programmable gate array (FPGA) circuitry is configured to provide emulated hardware device circuitry and a second portion of the FPGA circuitry is configured to provide power monitoring circuitry. The emulated hardware device circuitry and the power monitoring circuitry are coupled to FPGA power distribution network circuitry. The power monitoring circuitry includes time-to-digital converter (TDC) circuitry that includes observation delay buffers to sample a clock propagation delay. Since the voltage supplied to the buffer circuitry affects the propagation delay, the TDC circuitry outputs a binary sequence representative of one or more power delivery parameters to the emulated hardware device circuitry.

Abstract: Aspects disclosed in the detailed description include a microprocessor fault detection and response system. The microprocessor fault detection and response system utilizes a hardware-based fault-attack aware microprocessor extension (FAME) and a software-based trap handler for detecting and responding to a fault injection on a microprocessor. Upon detecting the fault injection, the hardware FAME switches the microprocessor from a normal mode to a safe mode and instructs the microprocessor to invoke the software-based trap handler in the safe mode. The hardware-based FAME provides fault recovery information to the software-based trap handler via a fault recovery register (FRR) for restoring the microprocessor to a fault-free state. By utilizing a combination of the hardware-based FAME and the software-based trap handler, it is possible to effectively protect the microprocessor from malicious fault attacks without significantly increasing performance and area overheads.