Abstract: Content-addressable memory-in-display (CAMiD) electronic displays and circuitry are provided. An electronic display may include a pixel active array and content-addressable control cells to control display pixels of the pixel active array using control signals propagated to the pixel active array on column lines by column driver circuits of the content-addressable control cells.

Abstract: Content-addressable memory-in-display (CAMiD) electronic displays and circuitry are provided. An electronic display may include a pixel active array to display an image frame over a series of subframes content-addressable control circuitry. The content-addressable control circuitry may control the pixel active array. The content-addressable control circuitry may include circuitry to perform subframe dithering to generate control signals to control the display pixels of the pixel active array. The control signals may correspond to different gray levels for different subframes of the series of subframes of the image frame to be displayed on the pixel active array.

Abstract: Content-addressable memory-in-display (CAMiD) electronic displays and circuitry are provided. An electronic display may include a pixel active array and content-addressable memory configured to selectively control the pixel active array.

Abstract: Content-addressable memory-in-display (CAMiD) electronic displays and circuitry are provided. An electronic display may include a pixel active array and a number of content-addressable control cells. Each control cell controls a respective display pixel of the pixel active array. Each control cell includes a comparator to generate a control signal to control the respective display pixel of the pixel active array based on a comparison between pixel data for the respective display pixel and one or more counters corresponding to a gray level.

Abstract: A stacked chip assembly for a display system may include a front plane die and one or more backplane dies, such as a first backplane die and a second backplane die. The front plane die may include a plurality of light emitting diodes (LEDs). The one or more backplane dies may be stacked vertically relative to the front plane die. In some implementations, the first backplane die may include a first portion of metal oxide semiconductor field effect transistor (MOSFET) display circuitry coupled with the plurality of LEDs, and the second backplane die may include a second portion of MOSFET display circuitry coupled with the first portion of MOSFET display circuitry. In some implementations, the backplane die may include display circuitry that is partitioned between analog circuitry in a first layer and digital circuitry in a second layer. Other aspects are also described and claimed.

Abstract: A pixel circuit for an electronic display may include a memory to store a digital data signal indicative of a value within a data range. The pixel circuit may also include a light-emitting diode to emit light based at least in part on the digital data signal. The pixel circuit may also include an initialization transistor to initialize the pixel circuit before the light-emitting diode emits light and a driving transistor to activate based at least in part on the digital data signal.

Abstract: A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

Abstract: In a display driver circuit, a push-pull circuit is coupled to an internal circuit, a first external power terminal, a second external power terminal and a target node respectively, and can control the on-off of the first external power terminal, the second external power terminal and the target node in response to a target control signal transmitted by the internal circuit. The switching circuit is coupled to the target node and the I/O interface of the display driver circuit respectively, and can transmit an electric potential of the target node to the I/O interface of the display driver circuit, that is, a first power signal transmitted from the first external power terminal to the target node or a second power signal transmitted from the second external power terminal to the target node is further output to the I/O interface.

Abstract: A pixel circuit for an electronic display may include a memory to store a digital data signal indicative of a value within a data range. The pixel circuit may also include a light-emitting diode to emit light based at least in part on the digital data signal. The pixel circuit may also include an initialization transistor to initialize the pixel circuit before the light-emitting diode emits light and a driving transistor to activate based at least in part on the digital data signal.

Abstract: A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

Abstract: A device may include an electronic display to display image frames. The display may include illuminators that generate light and mirrors that selectively direct the light to pixel locations based bitplanes that set the arrangement of the mirrors. Additionally, the device may include duty cycle balancing circuitry that generates and provides duty cycle balancing signals to the electronic display. In response to the duty cycle balancing signals, the electronic display is implements balancing on bitplanes during at least a first portion of off periods during the image frames and implements balancing off bitplanes during at least a second portion of the off periods such that, in the aggregate, a ratio of respective on times of the mirrors to respective off times of the mirrors is balanced across the image frames during the off periods.

Abstract: In a display driver circuit, a push-pull circuit is coupled to an internal circuit, a first external power terminal, a second external power terminal and a target node respectively, and can control the on-off of the first external power terminal, the second external power terminal and the target node in response to a target control signal transmitted by the internal circuit. The switching circuit is coupled to the target node and the I/O interface of the display driver circuit respectively, and can transmit an electric potential of the target node to the I/O interface of the display driver circuit, that is, a first power signal transmitted from the first external power terminal to the target node or a second power signal transmitted from the second external power terminal to the target node is further output to the I/O interface.

Abstract: A device may include an electronic display to display image frames. The display may include illuminators that generate light and mirrors that selectively direct the light to pixel locations based bitplanes that set the arrangement of the mirrors. Additionally, the device may include duty cycle balancing circuitry that generates and provides duty cycle balancing signals to the electronic display. In response to the duty cycle balancing signals, the electronic display is implements balancing on bitplanes during at least a first portion of off periods during the image frames and implements balancing off bitplanes during at least a second portion of the off periods such that, in the aggregate, a ratio of respective on times of the mirrors to respective off times of the mirrors is balanced across the image frames during the off periods.

Abstract: A pixel circuit for an electronic display may include a memory to store a digital data signal indicative of a value within a data range. The pixel circuit may also include a light-emitting diode to emit light based at least in part on the digital data signal. The pixel circuit may also include an initialization transistor to initialize the pixel circuit before the light-emitting diode emits light and a driving transistor to activate based at least in part on the digital data signal.

Abstract: A pixel circuit for an electronic display may include a memory to store a digital data signal indicative of a value within a data range. The pixel circuit may also include a light-emitting diode to emit light based at least in part on the digital data signal. The pixel circuit may also include an initialization transistor to initialize the pixel circuit before the light-emitting diode emits light and a driving transistor to activate based at least in part on the digital data signal.

Abstract: A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

Abstract: A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

Abstract: Efficiently transmitting image data to an electronic display may be provided by skipping regions of the electronic display that display a default value. The electronic display may include a number of pixels, a row driver, and a data driver. The row driver may activate a first subset of the pixels for programming. The data driver may program a default pixel value to respective pixels of the first subset of the pixels for which image data has not been received and may program image data to respective pixels of the first subset of the pixels for which image data has been received.

Abstract: A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

Abstract: An electronic display may include an active area having a first pixel formed in the active area, where the first pixel emits light in response to image data. The electronic display may also include a controller to transmit the image data to the first pixel. The first pixel may include an organic light-emitting diode that emits the light in response to the image data, memory to digitally store the image data received from the controller, and driver circuitry to receive the image data from the memory. The driver circuitry may cause the organic light-emitting diode to emit the light in response to the image data.