Patents by Inventor Bill H. Nale

Bill H. Nale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210312972
    Abstract: A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 7, 2021
    Inventors: Arvind A. Kumar, James Alexander McCall, Bill H. Nale, John R. Goles, Dean-Dexter R. Eugenio
  • Patent number: 7454586
    Abstract: Data regarding physical parameters and security and commands to send such data can be communicated between a memory device and a memory controller using a memory bus connected between the two. In one embodiment, the invention includes receiving a first command at a memory device on a memory bus, the first command being other than a read or write command, and receiving a second command together with the first command, the second command to be initiated using lines that are not used by the first command.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: November 18, 2008
    Assignee: Intel Corporation
    Inventors: Jun Shi, Sandeep Jain, Animesh Mishra, Kuljit Bains, David Wyatt, Thomas D. Skelton, Bill H. Nale
  • Patent number: 7188208
    Abstract: Generating a pair of buses, each coupled to a common terminating device, each having a set of address signal lines that are coupled to a separate memory device, and driving one set of address signal lines with an address driven with true logic states while driving the other set of address signal lines with the same address, but driven to opposing logic states, to achieve a greater balance between the quantity of signals across both buses that are driven to a high state versus those that are driven to a low state.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: March 6, 2007
    Assignee: Intel Corporation
    Inventors: Howard S. David, Bill H. Nale