Abstract: A nanopore measurement circuit includes a first analog memory configured to store a first electrical value corresponding to a first measurement sample of a nanopore and a second analog memory configured to store a second electrical value corresponding to a second measurement sample of the nanopore. The nanopore measurement circuit also includes a measurement circuitry configured to provide an output indicating a difference between the first electrical value of the first analog memory and the second electrical value of the second analog memory.

Abstract: A nanopore measurement circuit includes a first analog memory configured to store a first electrical value corresponding to a first measurement sample of a nanopore and a second analog memory configured to store a second electrical value corresponding to a second measurement sample of the nanopore. The nanopore measurement circuit also includes a measurement circuitry configured to provide an output indicating a difference between the first electrical value of the first analog memory and the second electrical value of the second analog memory.

Abstract: A system includes a circuit configured to detect a voltage corresponding to an electrical measurement of a nanopore. The system also includes a component configured to compare the voltage to another voltage. Based at least in part on the comparison, a one bit indicator is determined. The one bit indicator indicates whether the voltage indicates a change in a state of the nanopore. In the event it is determined that the voltage indicates the change in the state of the nanopore, a multiple bit signal is provided for output.

Abstract: A system includes a circuit configured to detect a voltage corresponding to an electrical measurement of a nanopore. The system also includes a component configured to compare the voltage to another voltage. Based at least in part on the comparison, a one bit indicator is determined. The one bit indicator indicates whether the voltage indicates a change in a state of the nanopore. In the event it is determined that the voltage indicates the change in the state of the nanopore, a multiple bit signal is provided for output.

Abstract: A nanopore measurement circuit includes a first analog memory configured to store a first electrical value corresponding to a first measurement sample of a nanopore and a second analog memory configured to store a second electrical value corresponding to a second measurement sample of the nanopore. The nanopore measurement circuit also includes a measurement circuitry configured to provide an output indicating a difference between the first electrical value of the first analog memory and the second electrical value of the second analog memory.

Abstract: A nanopore measurement circuit includes a first analog memory configured to store a first electrical value corresponding to a first measurement sample of a nanopore and a second analog memory configured to store a second electrical value corresponding to a second measurement sample of the nanopore. The nanopore measurement circuit also includes a measurement circuitry configured to provide an output indicating a difference between the first electrical value of the first analog memory and the second electrical value of the second analog memory.

Abstract: A nanopore measurement circuit includes a first analog memory configured to store a first electrical value corresponding to a first measurement sample of a nanopore and a second analog memory configured to store a second electrical value corresponding to a second measurement sample of the nanopore. The nanopore measurement circuit also includes a measurement circuitry configured to provide an output indicating a difference between the first electrical value of the first analog memory and the second electrical value of the second analog memory.

Abstract: A nanopore measurement circuit is disclosed. The nanopore measurement circuit includes a nanopore electrode, a first analog memory and a second analog memory. The nanopore measurement circuit also includes a switch network that selectively connects the nanopore electrode to at least one of the first analog and the second analog memory.

Abstract: A system includes a plurality of nanopore cells. Data corresponding to nanopore states of the plurality of nanopore cells is received. The data is analyzed to determine a compressed output size of the data given at least one compression technique. It is determined whether the compressed output size exceeds a data budget. In the event it is determined that the compressed output size exceeds the data budget, the data is modified. The modified data is outputted.

Abstract: A method of analyzing a molecule is disclosed. A voltage source is selectively connected to or disconnected from a capacitor using a switch controlled by a reset signal. A charge is stored in a capacitor when the voltage source is connected to the capacitor. The capacitor is discharged through a nanopore in a membrane when the voltage source is disconnected from the capacitor. A duty cycle of the reset signal is determined such that the voltage source and the capacitor is connected for at least a one tenth portion of a reset signal period and disconnected for a remaining portion of the reset signal period, such that a voltage across the nanopore is maintained at a higher level during the portion of the reset signal period in which the connection is maintained than during the remaining portion of the reset signal period in which the connection is not maintained.

Abstract: A nanopore based sequencing chip package is disclosed. The nanopore based sequencing chip package includes a reservoir defined by a plurality of surfaces. The chip package includes a nanopore cell array comprising a plurality of nanopore sensor cells enclosed by the reservoir. Each nanopore sensor cell has a working electrode. At least one surface of the reservoir is configured to be in contact with a conducting fluid when the conducting fluid is flowing through the reservoir. The chip package further includes a counter electrode disposed on the at least one surface of the reservoir.

Abstract: A nanopore measurement circuit is disclosed. The nanopore measurement circuit includes a nanopore electrode, a first analog memory and a second analog memory. The nanopore measurement circuit also includes a switch network that selectively connects the nanopore electrode to at least one of the first analog and the second analog memory.

Abstract: A system includes a plurality of nanopore cells. Data corresponding to nanopore states of the plurality of nanopore cells is received. The data is analyzed to determine a compressed output size of the data given at least one compression technique. It is determined whether the compressed output size exceeds a data budget. In the event it is determined that the compressed output size exceeds the data budget, the data is modified. The modified data is outputted.

Abstract: A system includes a circuit configured to detect a voltage corresponding to an electrical measurement of a nanopore. The system also includes a component configured to compare the voltage to another voltage. Based at least in part on the comparison, a one bit indicator is determined. The one bit indicator indicates whether the voltage indicates a change in a state of the nanopore. In the event it is determined that the voltage indicates the change in the state of the nanopore, a multiple bit signal is provided for output.

Abstract: A method of analyzing a molecule in a nanopore is disclosed. A voltage is applied across a nanopore that is inserted in a membrane by coupling the nanopore to a voltage source. The nanopore is decoupled from the voltage source. After the decoupling, a rate of decay of the voltage across the nanopore is determined. A molecule in the nanopore is distinguished from other possible molecules based on the determined rate of decay of the voltage across the nanopore.

Abstract: A method of analyzing a molecule in a nanopore is disclosed. A voltage is applied across a nanopore that is inserted in a membrane by coupling the nanopore to a voltage source. The nanopore is decoupled from the voltage source. After the decoupling, a rate of decay of the voltage across the nanopore is determined. A molecule in the nanopore is distinguished from other possible molecules based on the determined rate of decay of the voltage across the nanopore.

Abstract: A method of analyzing a molecule is disclosed. A voltage source is selectively connected to or disconnected from a capacitor using a switch controlled by a reset signal. A charge is stored in a capacitor when the voltage source is connected to the capacitor. The capacitor is discharged through a nanopore in a membrane when the voltage source is disconnected from the capacitor. A duty cycle of the reset signal is determined such that the voltage source and the capacitor is connected for at least a one tenth portion of a reset signal period and disconnected for a remaining portion of the reset signal period, such that a voltage across the nanopore is maintained at a higher level during the portion of the reset signal period in which the connection is maintained than during the remaining portion of the reset signal period in which the connection is not maintained.

Abstract: A nanopore based sequencing chip package is disclosed. The nanpore based sequencing chip package includes a reservoir defined by a plurality of surfaces. The chip package includes a nanopore cell array comprising a plurality of nanopore sensor cells enclosed by the reservoir. Each nanopore sensor cell has a working electrode. At least one surface of the reservoir is configured to be in contact with a conducting fluid when the conducting fluid is flowing through the reservoir. The chip package further includes a counter electrode disposed on the at least one surface of the reservoir.

Abstract: Current sensing circuits having independently adjustable dual-level trip thresholds for use in hot swap controllers, solid state circuit breakers and other current sensing circuits. The dual-level trip threshold is user-programmable to provide one current level for power-up conditions and another current level for normal operation. The two separate thresholds are also useful during normal operation to monitor both the steady state current and to set a limit on the upper current which should never be exceeded. Various features and alternate embodiments are disclosed.