Abstract: An order controller stores each received event in a separate entry in one of at least two queues with a separate counter value set from an arrival order counter at the time of storage, wherein the arrival order counter is incremented after storage of each of the received events and on overflow the arrival order counter wraps back to zero. The order controller calculates an absolute value of the difference between a first counter value stored with an active first next entry in a first queue from among the at least two queues and a second counter value stored with an active second next entry in a second queue from among the at least two queues. The order controller compares the absolute value with a counter midpoint value to determine whether the first counter value was stored before the second counter value.

Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Abstract: An order controller stores each received event in a separate entry in one of at least two queues with a separate counter value set from an arrival order counter at the time of storage, wherein the arrival order counter is incremented after storage of each of the received events and on overflow the arrival order counter wraps back to zero. The order controller calculates an absolute value of the difference between a first counter value stored with an active first next entry in a first queue from among the at least two queues and a second counter value stored with an active second next entry in a second queue from among the at least two queues. The order controller compares the absolute value with a counter midpoint value to determine whether the first counter value was stored before the second counter value.

Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Abstract: This invention relates to a use of G-CSF dimer in the treatment of neutropenia. In particular, the recombinant human G-CSF of the present invention can enhance the differentiation and development of neutrophils in animal, and thus effectively reduce the severity of the severe neutropenia and shorten the time of severe neutropenia for the post-chemotherapy cancer patients. Serum half-life of G-CSF dimer of this invention is prolonged and the biological activity thereof is increased, providing a better effect in the treatment of neutropenia.

Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Abstract: A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.

Abstract: A logic unit is configured with least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles. The logic unit is configured with at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.

Abstract: A constrained prosthetic knee having a modular hinge post and a rotating bearing. A cannulated hinge post is rotatably connected to the femoral component of the knee prosthesis so that a hinge post extension may be anteriorly positioned through the hinge post and into the tibial component of the knee prosthesis, after positioning of the femoral component in the femur and the tibial component in the tibia. The hinge post is preassembled to the femoral component so that such assembly is not required during the implantation procedure. A meniscal component forming the rotating bearing of the knee prosthesis is packaged together with the hinge post extension so that the appropriate hinge post extension is readily available. The meniscal component includes a mechanism for preventing lift off of the meniscal component from the tibial component, while allowing rotation of the meniscal component relative to the tibial component.

Abstract: A logic unit is configured with least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles. The logic unit is configured with at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.

Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Abstract: An order controller stores each received event in a separate entry in one of at least two queues with a separate counter value set from an arrival order counter at the time of storage, wherein the arrival order counter is incremented after storage of each of the received events and on overflow the arrival order counter wraps back to zero. The order controller calculates an absolute value of the difference between a first counter value stored with an active first next entry in a first queue from among the at least two queues and a second counter value stored with an active second next entry in a second queue from among the at least two queues. The order controller compares the absolute value with a counter midpoint value to determine whether the first counter value was stored before the second counter value.

Abstract: This invention relates to a recombinant human G-CSF (rhG-CSF) dimer and its use in the treatment of neurological disorder. In particular, upon ischemic neural injury in animal, this invention can be used to protect neurons with the use of rhG-CSF dimer such that function of injured nerves can be restored. Serum half-life of G-CSF dimer of this invention is prolonged and the biological activity thereof is increased.

Abstract: This invention relates to a recombinant human G-CSF (rhG-CSF) dimer and its use in the treatment of neurological disorder. In particular, upon ischemic neural injury in animal, this invention can be used to protect neurons with the use of rhG-CSF dimer such that function of injured nerves can be restored. Serum half-life of G-CSF dimer of this invention is prolonged and the biological activity thereof is increased.

Abstract: The automation of design and sale of electronic and mechanical components is accomplished by allowing a user to design a plan for their electronic and mechanical component needs using specialized software. The software utilizes predefined models of components to aid the user in designing a system where all the components are compatible, even in cases where the components are made by different manufacturers. This is accomplished by creating a model for each proposed piece of equipment in the system, the model having properties and rules, wherein the rules define conditions and actions. Then an object is created for each piece of equipment in the system. Selections for values for the properties are received for each of the pieces of equipment. Any rules that have as a condition the properties for which value selections are received are executed. Finally, testing may be undertaken to determine if a proposed configuration is valid by examining results of the rule execution.

Abstract: This invention relates to a use of G-CSF dimer in the treatment of neutropenia. In particular, the recombinant human G-CSF of the present invention can enhance the differentiation and development of neutrophils in animal, and thus effectively reduce the severity of the severe neutropenia and shorten the time of severe neutropenia for the post-chemotherapy cancer patients. Serum half-life of G-CSF dimer of this invention is prolonged and the biological activity thereof is increased, providing a better effect in the treatment of neutropenia.

Abstract: A constrained prosthetic knee having a modular hinge post and a rotating bearing. A cannulated hinge post is rotatably connected to the femoral component of the knee prosthesis so that a hinge post extension may be anteriorly positioned through the hinge post and into the tibial component of the knee prosthesis, after positioning of the femoral component in the femur and the tibial component in the tibia. The hinge post is preassembled to the femoral component so that such assembly is not required during the implantation procedure. A meniscal component forming the rotating bearing of the knee prosthesis is packaged together with the hinge post extension so that the appropriate hinge post extension is readily available. The meniscal component includes a mechanism for preventing lift off of the meniscal component from the tibial component, while allowing rotation of the meniscal component relative to the tibial component.

Abstract: A constrained prosthetic knee having a modular hinge post and a rotating bearing. A cannulated hinge post is rotatably connected to the femoral component of the knee prosthesis so that a hinge post extension may be anteriorly positioned through the hinge post and into the tibial component of the knee prosthesis, after positioning of the femoral component in the femur and the tibial component in the tibia. The hinge post is preassembled to the femoral component so that such assembly is not required during the implantation procedure. A meniscal component forming the rotating bearing of the knee prosthesis is packaged together with the hinge post extension so that the appropriate hinge post extension is readily available.