Abstract: The present invention describes a circuit for performing high speed forward Scaled Discrete Cosine Transform (SDCT) and inverse Scaled Discrete Cosine Transform (ISDCT) in pipeline architecture which is ideally, but not exclusively, used for compressing and decompressing large volume image data in real time. A high throughput of image data transform and inverse transform is achieved with a relatively slow internal clock. The four stage pipeline architecture of the present invention requires no more than five multipliers in rendering either the forward SDCT or inverse SDCT coefficients. The lower-order SDCT's for either the forward or the inverse direction are imbedded in the higher-order forward SDCT or inverse SDCT respectively. By taking advantage of the recursive properties of the SDCT's, a larger size SDCT can be always implemented by using a combination of variants of smaller size SDCT.