Abstract: A semiconductor package including a bottom leadframe having a bottom plate portion and a first terminal extending from the bottom plate portion, and a second terminal being co-planar with the first terminal. The semiconductor package also comprises a semiconductor power enhancement mode JFET die having a bottom surface and a top surface on which a first metalized region and a second metalized region are disposed. The bottom surface of the JFET die is coupled to the bottom plate of the leadframe. The semiconductor package also comprises a copper plate coupled to and spanning a substantial part of the first metalized region, and at least one beam portion sized and shaped to couple the copper plate portion to the second terminal such that it is electrically coupled to the source.