Patents by Inventor Bill Podkowa

Bill Podkowa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Timekeeping comparison circuitry and dual storage memory cells to detect alarms
    Patent number: 5544078
    Abstract: A low-power integrated circuit clock/calendar, wherein separate data busses are used for the time data and the alarm data. Conditional logic is used to only compare seconds bits (unless a match occurs, in which case higher-order bits are then compared). Thus, charging and discharging of the data busses (which carry the time data) occurs only when a data transition is occurring. A special clocked latch circuit is used to hold the potential of each line of the time data bus constant, except when the data on the bus is actually changing. These innovations help to provide extremely long battery lifetime, since charge is not consumed by unnecessarily charging and discharging busses. Preferably this bus architecture is combined with a low-power logic architecture.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: August 6, 1996
    Assignee: Dallas Semiconductor Corporation
    Inventor: Bill Podkowa
  • Precharge circuitry and bus for low power applications
    Patent number: 5347472
    Abstract: A low-power integrated circuit clock/calendar, wherein separate data busses are used for the time data and the alarm data. Conditional logic is used to only compare seconds bits (unless a match occurs, in which case higher-order bits are then compared). Thus, charging and discharging of the data busses (which carrying the time data) occurs only when a data transition is occurring. A special clocked latch circuit is used to hold the potential of each line of the time data bus constant, except when the data on the bus is actually changing. These innovations help to provide extremely long battery lifetime, since charge is not consumed by unnecessarily charging and discharging busses. Preferably this bus architecture is combined with a low-power logic architecture.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: September 13, 1994
    Assignee: Dallas Semiconductor Corporation
    Inventor: Bill Podkowa
  • Precharge circuitry and bus for low power applications
    Patent number: 5003501
    Abstract: A low-power integrated circuit clock/calendar, wherein separate data busses are used for the time data and the alarm data. Conditional logic is used to only compare seconds bits (unless a match occurs, in which case higher-order bits are then compared). Thus, charging and discharging of the data busses (which carry the time data) occurs only when a data transition is occurring. A special clocked latch circuit is used to hold the potential of each line of the time data bus constant, except when the data on the bus is actually changing. These innovations help to provide extremely long battery lifetime, since charge is not consumed by unnecessarily charging and discharging busses. Preferably this bus architecture is combined with a low-power logic architecture.
    Type: Grant
    Filed: June 26, 1989
    Date of Patent: March 26, 1991
    Assignee: Dallas Semiconductor Corporation
    Inventor: Bill Podkowa