Patents by Inventor Bill W Bereza

Bill W Bereza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Heterogeneous transceiver architecture for wide range programmability of programmable logic devices
    Patent number: 8787352
    Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: July 22, 2014
    Assignee: Altera Corporation
    Inventors: Sergey Shumarayev, Bill W. Bereza, Chong H. Lee, Rakesh H. Patel, Wilson Wong
  • HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES
    Publication number: 20110211621
    Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
    Type: Application
    Filed: May 9, 2011
    Publication date: September 1, 2011
    Applicant: ALTERA CORPORATION
    Inventors: Sergey Shumarayev, Bill W. Bereza, Chong H. Lee, Rakesh H. Patel, Wilson Wong
  • Heterogeneous transceiver architecture for wide range programmability of programmable logic devices
    Patent number: 7940814
    Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: May 10, 2011
    Assignee: Altera Corporation
    Inventors: Sergey Shumarayev, Bill W. Bereza, Chong H. Lee, Rakesh H. Patel, Wilson Wong
  • HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES
    Publication number: 20100058099
    Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
    Type: Application
    Filed: October 9, 2009
    Publication date: March 4, 2010
    Applicant: ALTERA CORPORATION
    Inventors: Sergey Shumarayev, Bill W. Bereza, Chong H. Lee, Rakesh H. Patel, Wilson Wong
  • Heterogeneous transceiver architecture for wide range programmability of programmable logic devices
    Patent number: 7616657
    Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: November 10, 2009
    Assignee: Altera Corporation
    Inventors: Sergey Shumarayev, Bill W Bereza, Chong H Lee, Rakesh H Patel, Wilson Wong