Abstract: One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.

Abstract: Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 9° or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

Abstract: One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.

Abstract: Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 90 or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

Abstract: The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.

Abstract: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

Abstract: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

Abstract: The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.

Abstract: The present invention provides, in one embodiment, a method of forming an opening in a dielectric layer 150. In this embodiment, the method comprises forming a dielectric layer 150 over a target layer 130 located over a microelectronic substrate 110 and subjecting the dielectric layer 150 to a plasma etch 165 to form an opening 145 in the dielectric layer 150, wherein the plasma etch 165 is highly selective to the target layer 130, such that a selectivity of the dielectric layer 150 to the target layer 130 is at least about 18:1 and a dielectric etch rate of the plasma etch 165 is at least about 380 nm/min.

Abstract: A waste gas stream including halohydrocarbons is treated with a surface wave to form a cold plasma. Additional reaction gases can be mixed with the waste gas stream to improve the destruction of the halohydrocarbons. The apparatus for the treatment of gaseous halogenated organic and other persistent organic compounds includes a reaction vessel (12) in which the waste gas is exposed to the surface wave, thereby forming a non-thermal plasma. The apparatus further includes a means for mixing (7) the waste gases together with the appropriate ancillary reaction gases to facilitate formation of free radicals suited to treat a particular waste stream. Also, a means of introducing an appropriate mixture of waste gases and additive gases into the plasma reaction vessel where the halohydrocarbons are decomposed is provided. Since some reactions may produce solid material by-products that are not easily handled by suction pumps a means of trapping (13) these particles may be included in this apparatus.