Abstract: Certain embodiments enable application message delivery to be automatically guaranteed for all failover scenarios through use of a novel infrastructure layer that supports high availability (HA) messaging. The High Availability Application Messaging Layer (HAML) can guarantee delivery of application messages whether a failover occurs at one or both of the source and the intended destination of the message. The HAML may transmit messages to one intended destination, as unicast messaging, or to multiple intended destinations, as multicast messaging. In some embodiments, the HAML may be HA aware, which refers to the awareness of the HAML of the redundancy for all processing entities within a network device to ensure hitless failover at the network device. By moving support for HA messaging from individual applications to the HAML, as a common infrastructure layer across the processing entities, the individual applications do not need to implement additional software to explicitly support HA messaging.

Abstract: Certain embodiments enable application message delivery to be automatically guaranteed for all failover scenarios through use of a novel infrastructure layer that supports high availability (HA) messaging. The High Availability Application Messaging Layer (HAML) can guarantee delivery of application messages whether a failover occurs at one or both of the source and the intended destination of the message. The HAML may transmit messages to one intended destination, as unicast messaging, or to multiple intended destinations, as multicast messaging. In some embodiments, the HAML may be HA aware, which refers to the awareness of the HAML of the redundancy for all processing entities within a network device to ensure hitless failover at the network device. By moving support for HA messaging from individual applications to the HAML, as a common infrastructure layer across the processing entities, the individual applications do not need to implement additional software to explicitly support HA messaging.

Abstract: Certain embodiments enable application message delivery to be automatically guaranteed for all failover scenarios through use of a novel infrastructure layer that supports high availability (HA) messaging. The High Availability Application Messaging Layer (HAML) can guarantee delivery of application messages whether a failover occurs at one or both of the source and the intended destination of the message. The HAML may transmit messages to one intended destination, as unicast messaging, or to multiple intended destinations, as multicast messaging. In some embodiments, the HAML may be HA aware, which refers to the awareness of the HAML of the redundancy for all processing entities within a network device to ensure hitless failover at the network device. By moving support for HA messaging from individual applications to the HAML, as a common infrastructure layer across the processing entities, the individual applications do not need to implement additional software to explicitly support HA messaging.

Abstract: Certain embodiments of the present invention provide techniques that enable messages to be sent to a processing entity within a computing device without knowing the network address of the processing entity. In certain embodiments, instead of using the network address of the processing entity, a message can be communicated to the processing entity using information indicative of a role or state or function performed by the processing entity.

Abstract: Techniques are disclosed for generating a multi-transactional system using transactional memory techniques. According to certain embodiments, a device may include a memory, one or more processing entities, and a transactional memory system for maintaining a plurality of transactional memory (TM) logs in a first portion of the memory. Each TM log may be associated with one transaction from a plurality of transactions sequentially executed by the one or more processing entities and each transaction comprises a plurality of operations. Furthermore, each TM log associated with each transaction comprises information associated with changes to a second portion of the memory caused by execution of operations from the transaction using the one or more processing entities. The TM logs for completed transactions may be used for error detection and recovery and maintaining high availability of the device.

Abstract: Certain embodiments of the present invention provide techniques that enable messages to be sent to a processing entity within a computing device without knowing the network address of the processing entity. In certain embodiments, instead of using the network address of the processing entity, a message can be communicated to the processing entity using information indicative of a role or state or function performed by the processing entity.

Abstract: Certain embodiments of the present invention provide techniques that enable messages to be sent to a processing entity within a computing device without knowing the network address of the processing entity. In certain embodiments, instead of using the network address of the processing entity, a message can be communicated to the processing entity using information indicative of a role or state or function performed by the processing entity.

Abstract: Techniques for persisting data stored in volatile memory across a warm boot. One or more portions (referred to as “warm memory”) of volatile memory of the system can be reserved and configured such that the data stored by these portions is not affected by a warm boot thereby resulting in the data stored being persisted across a warm boot.

Abstract: Techniques for achieving high-availability using a single processor (CPU). In a system comprising a multi-core processor, at least two partitions may be configured with each partition being allocated one or more cores of the multiple cores. The partitions may be configured such that one partition operates in active mode while another partition operates in standby mode. In this manner, a single processor is able to provide active-standby functionality, thereby enhancing the availability of the system comprising the processor.

Abstract: Techniques are provided for reliable and efficient access to non-transactional resources using transactional memory. In certain aspects, a device may include memory and one or more processing entities, configurable to execute a first transaction comprising one or more write operations to a first memory address, and a second transaction comprising one or more write operations to a second memory address. The first memory address and the second memory address may be mapped to the same controller for a hardware component and the one or more processing entities may commence execution of the second transaction after the first transaction starts execution and before the completion of the first transaction. The device may also include a transactional memory system configurable to communicate data written to the first memory address from the first transaction and the second memory address from the second transaction to the controller upon completion of the respective transactions.

Abstract: Techniques are disclosed for generating a multi-transactional system using transactional memory techniques. According to certain embodiments, a device may include a memory, one or more processing entities, and a transactional memory system for maintaining a plurality of transactional memory (TM) logs in a first portion of the memory. Each TM log may be associated with one transaction from a plurality of transactions sequentially executed by the one or more processing entities and each transaction comprises a plurality of operations. Furthermore, each TM log associated with each transaction comprises information associated with changes to a second portion of the memory caused by execution of operations from the transaction using the one or more processing entities. The TM logs for completed transactions may be used for error detection and recovery and maintaining high availability of the device.

Abstract: Techniques for facilitating high availability in a device (e.g., a network device) comprising redundant processing entities (e.g., one or more processors, one or more cores, etc.) and a transactional memory system. The transactional memory system comprises a memory that is shareable between the redundant processing entities and ensures consistency of information stored in the memory at the atomicity of a transaction. A first processing entity may operate in a first mode (e.g., active mode) while a second processing entity operates in a second mode (e.g., standby mode). Operational state information used by the active processing entity for performing a set of functions in the first mode may be stored in the shared memory. Upon a switchover, the second processing entity may start to operate in the first mode and commence performing the set of functions using the operational state information stored by the transactional memory system.

Abstract: Techniques for achieving high-availability using a single processor (CPU). In a system comprising a multi-core processor, at least two partitions may be configured with each partition being allocated one or more cores of the multiple cores. The partitions may be configured such that one partition operates in active mode while another partition operates in standby mode. In this manner, a single processor is able to provide active-standby functionality, thereby enhancing the availability of the system comprising the processor.

Abstract: Certain embodiments enable application message delivery to be automatically guaranteed for all failover scenarios through use of a novel infrastructure layer that supports high availability (HA) messaging. The High Availability Application Messaging Layer (HAML) can guarantee delivery of application messages whether a failover occurs at one or both of the source and the intended destination of the message. The HAML may transmit messages to one intended destination, as unicast messaging, or to multiple intended destinations, as multicast messaging. In some embodiments, the HAML may be HA aware, which refers to the awareness of the HAML of the redundancy for all processing entities within a network device to ensure hitless failover at the network device. By moving support for HA messaging from individual applications to the HAML, as a common infrastructure layer across the processing entities, the individual applications do not need to implement additional software to explicitly support HA messaging.

Abstract: Certain embodiments of the present invention provide techniques that enable messages to be sent to a processing entity within a computing device without knowing the network address of the processing entity. In certain embodiments, instead of using the network address of the processing entity, a message can be communicated to the processing entity using information indicative of a role or state or function performed by the processing entity.

Abstract: Certain embodiments enable resources assigned or allocated to an operating virtual machine (VM) to be modified while the VM is operating and without having to stop, restart, or reboot the VM. The modification may correspond to increasing or decreasing the amount of a resource being assigned to the VM. In this manner, resources assigned to a VM at the time of creation of the VM are not static and can instead be dynamically changed while the VM is operating without having to stop, reboot, or restart the VM. In some embodiments, the changes to the resources allocated to one or more VMs provided for a user (e.g., a customer) may be made according to or in response to a Service Level Agreement (SLA) entered into by the user, in response to an event such as a failover or switchover event, and the like.

Abstract: Techniques for achieving high-availability using a single processor (CPU). In a system comprising a multi-core processor, at least two partitions may be configured with each partition being allocated one or more cores of the multiple cores. The partitions may be configured such that one partition operates in active mode while another partition operates in standby mode. In this manner, a single processor is able to provide active-standby functionality, thereby enhancing the availability of the system comprising the processor.

Abstract: Techniques for achieving high-availability using a single processor (CPU). In a system comprising a multi-core processor, at least two partitions may be configured with each partition being allocated one or more cores of the multiple cores. The partitions may be configured such that one partition operates in active mode while another partition operates in standby mode. In this manner, a single processor is able to provide active-standby functionality, thereby enhancing the availability of the system comprising the processor.

Abstract: Techniques for persisting data stored in volatile memory across a warm boot. One or more portions (referred to as “warm memory”) of volatile memory of the system can be reserved and configured such that the data stored by these portions is not affected by a warm boot thereby resulting in the data stored being persisted across a warm boot.