Patents by Inventor Billie BI

Billie BI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Leadless semiconductor package and method of manufacture
    Patent number: 11631634
    Abstract: This disclosure relates to a leadless packaged semiconductor device including a top and a bottom opposing major surfaces and sidewalls extending between the top and bottom surfaces, the leadless packaged semiconductor device further includes a lead frame structure including an array of two or more lead frame sub-structures each having a semiconductor die arranged thereon, and terminals and a track extended across the bottom surface of the semiconductor device. The track provides a region for interconnecting the semiconductor die and terminals, and the track is filled by an insulating material to isolate the lead frame sub-structures.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: April 18, 2023
    Assignee: Nexperia B.V.
    Inventors: On Lok Chau, Fei Wong, Ringo Cheung, Billie Bi
  • SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20220262711
    Abstract: A semiconductor device is provided, including a lead frame, a metal pad and the metal pad is connected to a back side of the semiconductor device via the lead frame. The semiconductor device further includes a die pad, and the die pad is attached to the lead frame via a die attach material, and an encapsulant that is disposed on the top surface of the lead frame. The encapsulant isolates the metal pad from the die pad.
    Type: Application
    Filed: February 14, 2022
    Publication date: August 18, 2022
    Applicant: NEXPERIA B.V.
    Inventors: On Lok Chau, Fei Wong, William Hor, Billie Bi, Ivan Shiu
  • LEADLESS SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE
    Publication number: 20210287972
    Abstract: This disclosure relates to a leadless packaged semiconductor device including a top and a bottom opposing major surfaces and sidewalls extending between the top and bottom surfaces, the leadless packaged semiconductor device further includes a lead frame structure including an array of two or more lead frame sub-structures each having a semiconductor die arranged thereon, and terminals and a track extended across the bottom surface of the semiconductor device. The track provides a region for interconnecting the semiconductor die and terminals, and the track is filled by an insulating material to isolate the lead frame sub-structures.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 16, 2021
    Applicant: NEXPERIA B.V.
    Inventors: On Lok CHAU, Fei WONG, Ringo CHEUNG, Billie BI