Patents by Inventor Billie J. Rivera

Billie J. Rivera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for integrated circuit design with library cells
    Patent number: 7051308
    Abstract: Methods are apparatuses are disclosed for library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: May 23, 2006
    Assignee: Virtual Silicon Technology, Inc.
    Inventors: Michael J. McManus, Billie J. Rivera, Richard Talburt, William G. Walker, Michael A. Zampaglione
  • Method and apparatus for design of integrated circuits
    Patent number: 6839882
    Abstract: Methods are apparatuses are disclosed for an electrical apparatus. The electrical apparatus includes one or more integrated circuits designed at least partly with library cells. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: January 4, 2005
    Assignee: Virtual Silicon Technology, Inc.
    Inventors: Michael J. McManus, Billie J. Rivera, Richard Talburt, William G. Walker, Michael A. Zampaglione
  • Method and apparatus for integrated circuit design with a software tool
    Patent number: 6766496
    Abstract: Methods are apparatuses are disclosed for a software tool adapted to function with at least library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: July 20, 2004
    Assignee: Virtual Silicon Technology, Inc.
    Inventors: Michael J. McManus, Billie J. Rivera, Richard Talburt, William G. Walker, Michael A. Zampaglione
  • Method and apparatus for integrated circuit design with library cells
    Publication number: 20030023935
    Abstract: Methods are apparatuses are disclosed for library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.
    Type: Application
    Filed: June 3, 2002
    Publication date: January 30, 2003
    Inventors: Michael J. McManus, Billie J. Rivera, Richard Talburt, William G. Walker, Michael A. Zampaglione
  • Method and apparatus for integrated circuit design with a software tool
    Publication number: 20030023936
    Abstract: Methods are apparatuses are disclosed for a software tool adapted to function with at least library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.
    Type: Application
    Filed: June 3, 2002
    Publication date: January 30, 2003
    Inventors: Michael J. McManus, Billie J. Rivera, Richard Talburt, William G. Walker, Michael A. Zampaglione
  • Method and apparatus for design of integrated circuits
    Publication number: 20030023937
    Abstract: Methods are apparatuses are disclosed for an electrical apparatus. The electrical apparatus includes one or more integrated circuits designed at least partly with library cells. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.
    Type: Application
    Filed: June 3, 2002
    Publication date: January 30, 2003
    Inventors: Michael J. McManus, Billie J. Rivera, Richard Talburt, William G. Walker, Michael A. Zampaglione