Abstract: The System-on-Chip apparatus and integration methodology disclosed includes a single semiconductor integrated circuit having one or more processor subsystems, one or more DMA-type peripherals, and a Memory Access Controller (MAC) on a first internal unidirectional bus. The first internal unidirectional bus controls transactions between the processor subsystem(s) and the DMA peripheral(s) using a Memory Access Controller (MAC) and unidirectional, positive-edge clocked address and transaction control signals. The first internal unidirectional bus can support burst operation, variable-speed pipelined memory transactions, and hidden arbitration. The SoC may include a second internal unidirectional bus that controls transactions between the processor subsystem(s) and non-DMA peripherals. The second internal unidirectional bus controls transactions between the processor subsystem(s) and the non-DMA peripheral(s) using unidirectional address and transaction control signals.

Abstract: A system resource router interfaces initiators through protocol-adapting sockets to a plurality of sub-buses. A switch matrix allows at least some of the sockets to be connected to two or more of the sub-buses. Each sub-bus interfaces through a channel controller to target devices like memory and peripherals. A graphical user interface, assembly program, and computer-aided design platform allow users to customize system resource router configurations for particular applications. At least one embodiment produces Verilog or other hardware description language intellectual property technology libraries. It implements the optimal mix of sub-buses, switches, sockets, and controllers that will be needed for a particular user application.

Abstract: The System-on-Chip apparatus and integration methodology disclosed includes a single semiconductor integrated circuit having one or more processor subsystems, one or more DMA-type peripherals, and a Memory Access Controller (MAC) on a first internal unidirectional bus. The first internal unidirectional bus controls transactions between the processor subsystem(s) the MAC, and the DMA peripheral(s) using a single centralized address decoder and unidirectional, positive-edge clocked address and transaction control signals. The first internal unidirectional bus can support burst operation, variable-speed pipelined memory transactions, and hidden arbitration. The SoC may include a second internal unidirectional bus that controls transactions between the processor subsystem(s) and non-DMA peripherals. The second internal unidirectional bus controls transactions between the processor subsystem(s) and the non-DMA peripheral(s) using unidirectional address and transaction control signals.

Abstract: A system-on-chip interconnection structure and method uses unidirectional buses only, central shared memory controllers, separate interconnects for high-speed and low-speed peripherals, zero wait-state register accesses, application-specific memory map and peripherals, application-specific test methodology, allowances for cache controllers, and good fits with standard ASIC flow and tools.

Abstract: A system resource router interfaces initiators through protocol-adapting sockets to a plurality of sub-buses. A switch matrix allows at least some of the sockets to be connected to two or more of the sub-buses. Each sub-bus interfaces through a channel controller to target devices like memory and peripherals. A graphical user interface, assembly program, and computer-aided design platform allow users to customize system resource router configurations for particular applications. At least one embodiment produces Verilog or other hardware description language intellectual property technology libraries. It implements the optimal mix of sub-buses, switches, sockets, and controllers that will be needed for a particular user application.

Abstract: An improvement in a switching state retention circuit of adding a shunt capacitance across an inverter output in a selectable feedback loop. The circuit has a controlled inverter connected to both the selectively connected feedback loop and an output inverter. The shunt capacitance is across an inverter in the feedback loop to control propagation delay therearound without slowing state changes at the output of the circuit.