Abstract: A predriver circuit for current switching, di/dt, noise control for high current load devices is disclosed. Parallel weak pull up and pull down circuit paths are combined with strong pull up and pull down circuit paths, respectively, to provide control over the rate of change of current through the load during predetermined turn-on and turn-off time periods. Predriver control for both NMOS driver, current sink NMOS, and PMOS driver, current source PMOS, are demonstrated. The predriver circuit provides control of the rate of current switching through the load without excessive delay in fully turning on or off the load device.

Abstract: An integrated circuit process, voltage and temperature fluctuation self-aligning internal delay line circuit and method of operation. A PVT related reference signal is compared to a set of reference signals generated from a system voltage. A delay line is varied based upon the comparison results, generating a delayed timing signal related to PVT fluctuations.

Abstract: A load adaptive pad driver for integrated circuits provides a substantially constant speed output at the pad regardless of the load connected to the pad. A reference slope signal, based on variables such as fabrication process, and operational voltage and temperature ranges and biased to give a substantially flat response, is compared to the signal output of a resistive-based pad driver circuit. When a transition between output signal levels provided by the pad driver circuit is slower than the reference signal slope, an auxiliary driver circuit is used to compensate. Electromagnetic interference is also reduced via said load adaptive pad driver.

Abstract: A programmable power supply for driving LEDS is disclosed that includes a reference current leg and a number of output current legs. Both the reference current leg and the output current legs are further comprised of a plurality of parallel driver FET-control FET pairs, in which the driver and control FETs are connected in series. The driver FETs are biased by a reference voltage that provides a predetermined maximum output current. The control FETs are individually selected to provide a controlled output current. The individual control voltage is either a positive voltage, which disables the control FET, or a predetermined cascode voltage that places the control FET at or into the high output impedance saturation conduction region.

Abstract: A power supply circuit for an LED print head has a reference current source connected to a printer system reference voltage for providing a second reference voltage for an individual, integrated circuit chip. The reference current source is controlled by an operational amplifier, the output of which comprises the second reference voltage. A plurality of output driver FETs are biased by the reference voltage. Each output driver FET provides current to an associated LED responsive to a data signal. A plurality of control FETs are connected in parallel with each other and in series with each output driver FET for varying the LED output current responsive to programming data signals. A second group of control FETs is interposed in the feedback loop of the operational amplifier for varying the second reference voltage responsive to a different set of programming data signals.

Abstract: A power supply circuit for an LED print head has a reference current source connected to a printer system reference voltage for providing a second reference voltage for an individual, integrated circuit chip. A plurality of substantially similar field effect transistors have their gates connected to the chip reference voltage for providing substantially similar current to each of a plurality of light emitting diodes. The current is enabled to each such LED by the presence or absence of a data signal. A reference resistor in the reference current source permits adjustment so that each of a plurality of integrated circuit chips can provide substantially similar current to each of a plurality of LED dice, or adjust the current level, if required, to achieve similar light output from each LED.

Abstract: A binary adder employs separate summing and carry circuitry within each digit to optimize the speed of operation of the adder. Carry bits of less significant digits are calculated independently of corresponding sum bits, thus allowing propagation of such carry bits to more significant digits before completion of the summation of the less significant digits.