Abstract: A microcomputer surveillance system is operative to monitor the output signal of a power supply to determine if an alarm limit has been reached and to center the alarm limits around an operating point of the power supply. Sensed output signals are converted to signal frequencies and transmitted optically to counters which accumulate counts indicative of the output signal. A microcomputer controller uses these counts to set alarm limits and determine if an alarm limit has been exceeded.

Abstract: A waveform synthesizer is controlled in response to a stored program control utilizing tabular data stored in memory as the basis for generating timing signals to drive the power switching devices of the synthesizer. A plurality of tables of differing modulation indices define rated current output and a below rated current output. The table defines rated level output timing signals as both pulse width and frequency modulated to reduce harmonics. Various overload conditions result in selection of different modulation indices or a total current shutdown. A high peak current overload results in a halt in a progressive upward selection of modulation indices during start-up. A high average current overload results in a reduction in modulation indices until the overload has cleared.

Abstract: A pulse-width modulated current regulator (FIG. 4) includes a current flare out control (406,407,409,412) to limit current output at low output voltages. Current variation in an output filter inductor (408) is monitored and compared with a reference standard (407). A conduction interval is controlled in response to the comparison in order to limit current flare out.

Abstract: A plurality of current controlled converters coupled in parallel are controlled by a central regulation circuit. Each individual converter includes an auxiliary regulation circuit which is coupled to provide backup regulation if the central regulation circuit fails. The auxiliary regulation circuit has high and low response limits which come into action depending upon whether the central regulation fails in a high or low mode. This permits the converter to remain operative and continue to regulate its output within a predefined backup limit when the central regulation circuit fails.

Abstract: A control arrangement for a three-phase, uninterruptible power supply generates timing signals to drive the static switches of inverters located in each phase. This control arrangement precisely controls the phase differences of the inverter signals with relation to each other so that while the overall three-phase power supplied by the inverters is nulled, power circulation through the inverters compensates for unbalanced output loads thereby maintaining balanced phase angles between the output voltage and a balanced input impedance at the input of the power supply.