Abstract: A system that may optionally be partitioned into multiple domains is disclosed. Each domain is capable of independently powering on, executing a firmware program, and loading an operating system, including a legacy operating system, as well as running an application program that is distinct from programs running on another domain. Interrupts, including boot interrupts, reset handlers, and inter-chassis communications are initialized differently, depending on whether the system is to be partitioned or not. The cost of redundant hardware and/or firmware is substantially avoided, yet the system fully supports multiple domains.

Abstract: A multiprocessor computing apparatus that includes a mechanism for favoring at least one processor over another processor to achieve more equitable access to cached data. Logic for detecting when, for example, a remote and a local processor are attempting to access data from the cache of another local processor is disclosed. Logic that provides an advantage to the remote processor in a manner that achieves fairer access among the various processors is also disclosed.

Abstract: A computer baseboard providing localized support for high pin count, high density components. The baseboard includes a first circuit board capable of supporting low pin count electrical components. The first circuit board has a surface onto which the low pin count electrical components are mounted, and an area to which a second, smaller, circuit board is connected in a parallel arrangement with the first circuit board. The second circuit board has a first surface onto which high pin count electrical components are mounted, and a second surface physically and electrically connected to the area on said first substrate. The first and second circuit boards together provide support for electrical components having higher pin counts and densities than the first circuit board can support individually, such as high performance microprocessors and chipsets.

Abstract: An apparatus and method for using a circuit board as a heat sink for another circuit board which effectively draws heat away from the other circuit board while the one circuit board is actively producing its own heat. Since the one circuit board is much larger than the other circuit board, the thermal mass of the one circuit board is great enough to absorb and spread the heat generated by both boards in the presence of forced air cooling. The method includes the steps of mounting a thermal conductivity layer on a predetermined area on the one circuit board and mounting the other circuit board over the area on the one circuit board such that components on an underside of the other circuit board firmly contact the thermal conductivity layer so as to conduct heat from the components through the one circuit board.

Abstract: A device and method for generating a symmetrical clock signal. The device comprises a signal generator, buffer and differential amplifier. The signal generator generates a periodic wave signal. The buffer receives the periodic wave signal and provides a square wave clock signal. The differential amplifier receives the clock signal and a reference voltage signal and provides an error signal to the buffer.

Abstract: The subject invention is an interface circuit between a requesting device and a responding device. The circuit comprises a flip-flop responsive to a request signal received from the requesting device and a handshake signal received from the responding device to generate a control signal. The circuit also comprises a gate for receiving the control and handshake signals and generating an acknowledge signal. The removal of the request signal sets the control signal to a first value which disables the gate and removal of the handshake signal resets the control signal to a second value which enables the gate.

Abstract: A memory device is disclosed which is comprised of a plurality of memory boards each having at least one memory bank associated therewith with each memory bank including a plurality of memory elements addressable by rows and columns. In page-mode operation of the memory device, all of the memory elements receive the active row address strobe signal RAS. The RAS signal is maintained active as long as the memory is to remain in page-mode operation. Memory address information is decoded to select a memory board and a memory bank from the plurality of memory boards and to enable the memory elements to permit either a read or a write operation without the need for performing additional address strobe cycles.