Patents by Inventor Billy W. Garrett
Billy W. Garrett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9998305Abstract: An integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is an N-bit symbol, having one of 2N predefined values, N is an integer greater than 1, and the signal corresponding to the symbol has one of 2N signal levels. The driver circuit includes first, second and third driver sub-circuits, each driven by an input corresponding to one or more bits of the N-bit symbol, wherein the second and third driver sub-circuits are weighted, relative to the first driver sub-circuit, to reduce gds distortion in the signal.Type: GrantFiled: January 6, 2017Date of Patent: June 12, 2018Assignee: RAMBUS INC.Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, Jr., Carl W. Werner
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Publication number: 20170222845Abstract: An integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is an N-bit symbol, having one of 2N predefined values, N is an integer greater than 1, and the signal corresponding to the symbol has one of 2N signal levels. The driver circuit includes first, second and third driver sub-circuits, each driven by an input corresponding to one or more bits of the N-bit symbol, wherein the second and third driver sub-circuits are weighted, relative to the first driver sub-circuit, to reduce gds distortion in the signal.Type: ApplicationFiled: January 6, 2017Publication date: August 3, 2017Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, Carl W. Werner
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Patent number: 9544169Abstract: An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.Type: GrantFiled: January 17, 2014Date of Patent: January 10, 2017Assignee: RAMBUS INC.Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, Jr., Carl W. Werner
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Publication number: 20140286389Abstract: An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.Type: ApplicationFiled: January 17, 2014Publication date: September 25, 2014Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, JR., Carl W. Werner
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Patent number: 8634452Abstract: An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.Type: GrantFiled: June 7, 2012Date of Patent: January 21, 2014Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, Jr., Carl W. Werner
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Publication number: 20130010855Abstract: An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.Type: ApplicationFiled: June 7, 2012Publication date: January 10, 2013Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, JR., Carl W. Werner
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Patent number: 8199859Abstract: An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.Type: GrantFiled: October 4, 2010Date of Patent: June 12, 2012Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, Jr., Carl W. Werner
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Publication number: 20110140741Abstract: A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.Type: ApplicationFiled: October 4, 2010Publication date: June 16, 2011Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, JR., Carl W. Werner
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Patent number: 7809088Abstract: A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.Type: GrantFiled: November 23, 2009Date of Patent: October 5, 2010Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, Jr., Carl W. Werner
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Publication number: 20100134153Abstract: A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.Type: ApplicationFiled: November 23, 2009Publication date: June 3, 2010Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, JR., Carl W. Werner
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Patent number: 7626442Abstract: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.Type: GrantFiled: March 3, 2006Date of Patent: December 1, 2009Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, Jr., Carl W. Werner
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Patent number: 7536494Abstract: A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master device via the first bus and to transmit signals to the one or more slave devices via the second bus in response to the incoming signals, and a read buffer to receive outgoing signals from the one or more slave devices via the second bus and to transmit signals to the master device via the first bus in response to the outgoing signals.Type: GrantFiled: May 22, 2007Date of Patent: May 19, 2009Assignee: Rambus Inc.Inventors: Bruno W. Garlepp, Richard M. Barth, Kevin S. Donnelly, Ely K. Tsern, Craig E. Hampel, Jeffrey D. Mitchell, James A. Gasbarro, Billy W. Garrett, Jr., Fredrick A. Ware, Donald V. Perino
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Patent number: 7222209Abstract: A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.Type: GrantFiled: December 16, 2003Date of Patent: May 22, 2007Assignee: Rambus, Inc.Inventors: Bruno W. Garlepp, Richard M. Barth, Kevin S. Donnelly, Ely K. Tsern, Craig E. Hampel, Jeffrey D. Mitchell, James A. Gasbarro, Billy W. Garrett, Jr., Fredrick A. Ware, Donald V. Perino
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Patent number: 7170314Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.Type: GrantFiled: February 11, 2005Date of Patent: January 30, 2007Assignee: Rambus Inc.Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Jr., Ely Tsern, Crag E. Hampel, Wai-Yeng Yip
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Patent number: 7124221Abstract: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM sigsnals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.Type: GrantFiled: January 6, 2000Date of Patent: October 17, 2006Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, Jr., Carl W. Werner
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Patent number: 6898085Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.Type: GrantFiled: October 30, 2003Date of Patent: May 24, 2005Assignee: Rambus Inc.Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Jr., Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
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Publication number: 20040196064Abstract: A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.Type: ApplicationFiled: December 16, 2003Publication date: October 7, 2004Applicant: Rambus Inc.Inventors: Bruno W. Garlepp, Richard M. Barth, Kevin S. Donnelly, Ely K. Tsern, Craig E. Hampel, Jeffrey D. Mitchell, James A. Gasbarro, Billy W. Garrett, Fredrick A. Ware, Donald V. Perino
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Patent number: 6765800Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.Type: GrantFiled: April 20, 2001Date of Patent: July 20, 2004Assignee: Rambus Inc.Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Jr., Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
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Publication number: 20040105240Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.Type: ApplicationFiled: October 30, 2003Publication date: June 3, 2004Applicant: Rambus Inc.Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
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Patent number: 6687780Abstract: A bus system for use with addressable memory has a global bus of uni-directional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus. First and second global bus terminators are coupled to the first and second ends of the global bus, respectively. One or more subsystems are connected in parallel to each other and to the master device via the global bus. Each subsystem includes a local bus, one or more slave devices coupled to the local bus, a write buffer that receives incoming signals from the master device via the global bus and transmits the incoming signals to the one or more slave devices via the local bus, and a read buffer that receives outgoing signals from the one or more slave devices via the local bus and transmits the outgoing signals to the master device via the global bus.Type: GrantFiled: November 2, 2000Date of Patent: February 3, 2004Assignee: Rambus Inc.Inventors: Bruno W. Garlepp, Richard M. Barth, Kevin S. Donnelly, Ely K. Tsern, Craig E. Hampel, Jeffrey D. Mitchell, James A. Gasbarro, Billy W. Garrett, Jr., Fredrick A. Ware, Donald V. Perino