Patents by Inventor Billy Wayne Garrett, Jr.
Billy Wayne Garrett, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7352234Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: GrantFiled: January 22, 2007Date of Patent: April 1, 2008Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Nancy David Dillon, legal representative, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, John B. Dillon
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Patent number: 7167039Abstract: A method of operating an integrated circuit including an output driver. The method includes storing a value in a register, wherein the value is representative of a voltage swing setting of an output driver. The voltage swing setting of the output driver is adjusted using a counter that holds a count value representing an update to the voltage swing setting. The count value is updated in accordance with a signal that indicates an adjustment to the voltage swing setting. In addition, an integrated circuit memory device comprising an output driver, a register and a counter is provided. The counter updates a count value in response to a signal that indicates a direction to adjust the count value.Type: GrantFiled: July 14, 2004Date of Patent: January 23, 2007Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Nancy David Dillon, legal representative, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, John B. Dillon, deceased
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Patent number: 7039782Abstract: A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.Type: GrantFiled: October 20, 2003Date of Patent: May 2, 2006Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Frederick Abbott Ware, Craig E. Hampel, Richard M. Barth, Donald C. Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J. Sheffler, Ely K. Tsern, Steven Cameron Woo
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Patent number: 6975160Abstract: A system including an integrated circuit memory device. The integrated circuit device comprises a register to store a value representative of an output voltage setting. A circuit holds a value representative of an adjustment to the output voltage setting. An output driver outputs a drive voltage during a calibration operation, wherein a signal is generated based on a comparison between a signal derived from the drive voltage and a reference voltage. The signal updates the value representative of the adjustment to the output voltage setting.Type: GrantFiled: December 14, 2004Date of Patent: December 13, 2005Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Nancy David Dillon, legal representative, Michael Tak-Kei Ching, William E. Stonecynher, Andy Peng-Pui Chan, Matthew M. Griffin, John B. Dillon, deceased
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Patent number: 6975159Abstract: A method of operating a memory system that includes an integrated circuit memory device is provided. A value representing an output voltage setting of an output driver of the memory device is stored in a register. The output driver outputs the drive voltage. A signal derived from the drive voltage is compared to a reference signal to generate a signal that indicates an adjustment to the output voltage setting. The output voltage setting of the output driver is adjusted using a counter that holds a count value representing an update to the output voltage setting. The count value is updated in accordance with a signal that indicates the adjustment to the output voltage setting.Type: GrantFiled: November 5, 2004Date of Patent: December 13, 2005Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Nancy David Dillon, legal representative, Michael Tak-Kei Ching, William F. Stonecynher, Andy Peng-Pui Chan, Matthew M. Griffin, John B. Dillon, deceased
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Patent number: 6870419Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: GrantFiled: July 23, 2003Date of Patent: March 22, 2005Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Nancy David Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, John B. Dillon
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Patent number: 6839266Abstract: A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.Type: GrantFiled: March 20, 2002Date of Patent: January 4, 2005Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Frederick Abbott Ware, Craig E. Hampel, Richard M. Barth, Don Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J. Sheffler, Ely K. Tsern, Steven Cameron Woo
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Patent number: 6708248Abstract: A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.Type: GrantFiled: December 8, 1999Date of Patent: March 16, 2004Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., Frederick Abbott Ware, Craig E. Hampel, Richard M. Barth, Donald C. Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J. Sheffler, Ely K. Tsern, Steven Cameron Woo
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Patent number: 6608507Abstract: A memory system and method of adjusting an output driver characteristic of a memory device that is included in the memory system. The method includes providing a command to the memory device that specifies a calibration mode and, during the calibration mode, driving a voltage level onto the first signal line using a first output driver. A first voltage level is derived from an amount of voltage swing generated by the first output driver driving the voltage level onto the first signal line. The method also includes: actively coupling a first comparator to the first signal line; when the first comparator is coupled to the first signal line, comparing the first voltage level with a reference voltage using the first comparator; and adjusting the amount of voltage swing to arrive at a calibrated voltage swing level. In addition, the method includes actively isolation the first comparator from the first signal line upon exiting the calibration mode.Type: GrantFiled: August 29, 2002Date of Patent: August 19, 2003Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin
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Patent number: 6556052Abstract: A semiconductor controller device to control the operation of a semiconductor memory device. The controller device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. In addition, the controller device includes a voltage divider, coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. In addition, the controller device also includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.Type: GrantFiled: September 12, 2001Date of Patent: April 29, 2003Inventors: Billy Wayne Garrett, Jr., John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin
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Patent number: 6462591Abstract: A semiconductor memory device including an array of memory cells. The memory device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. The memory device further includes a voltage divider coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. The memory device further includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.Type: GrantFiled: June 14, 2001Date of Patent: October 8, 2002Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., John B. Dillon, by Nancy David Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin
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Patent number: 6370668Abstract: The present invention provides a high data bandwidth memory system capable of operating in non-chip-kill and chip-kill modes. In chip-kill mode, cycle multiplexing, bit multiplexing, and time and space multiplexing are used to read/write data and syndrome across a group of memory devices. Current command packet formats are adapted to communicate with the group of memory devices in chip-kill mode.Type: GrantFiled: September 14, 1999Date of Patent: April 9, 2002Assignee: Rambus INCInventors: Billy Wayne Garrett, Jr., Frederick Abbott Ware, Craig E. Hampel, Richard M. Barth, Don Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J. Sheffler, Ely K. Tsern, Steven Cameron Woo
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Patent number: 6294934Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: GrantFiled: April 26, 2000Date of Patent: September 25, 2001Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin
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Patent number: 6266730Abstract: A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time.Type: GrantFiled: February 18, 2000Date of Patent: July 24, 2001Assignee: Rambus Inc.Inventors: Donald V. Perino, Billy Wayne Garrett, Jr., Haw-Jyh Liaw, David Nguyen, Srinivas Nimmagadda, James A. Gasbarro, Richard DeWitt Crisp
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Patent number: 6094075Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: GrantFiled: August 27, 1998Date of Patent: July 25, 2000Assignee: Rambus IncorporatedInventors: Billy Wayne Garrett, Jr., John B. Dillon, deceased, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin
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Patent number: 6067594Abstract: A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time.Type: GrantFiled: September 26, 1997Date of Patent: May 23, 2000Assignee: Rambus, Inc.Inventors: Donald V. Perino, Billy Wayne Garrett, Jr., Haw-Jyh Liaw, David Nguyen, Srinivas Nimmagadda, James A. Gasbarro, Richard DeWitt Crisp
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Patent number: 5956284Abstract: Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access.Type: GrantFiled: October 6, 1998Date of Patent: September 21, 1999Assignee: Rambus Inc.Inventors: Frederick A. Ware, John B. Dillon, Richard M. Barth, Billy Wayne Garrett, Jr., John Girdner Atwood, Jr., Michael P. Farmwald, Richard DeWitt Crisp
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Patent number: 5940340Abstract: Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access.Type: GrantFiled: May 16, 1997Date of Patent: August 17, 1999Assignee: Rambus, Inc.Inventors: Frederick A. Ware, John B. Dillon, Richard M. Barth, Billy Wayne Garrett, Jr., John Girdner Atwood, Jr., Michael P. Farmwald, Richard DeWitt Crisp
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Patent number: 5844855Abstract: Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access.Type: GrantFiled: May 16, 1997Date of Patent: December 1, 1998Assignee: Rambus, Inc.Inventors: Frederick A. Ware, John B. Dillon, Richard M. Barth, Billy Wayne Garrett, Jr., John Girdner Atwood, Jr., Michael P. Farmwald, Richard DeWitt Crisp
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Patent number: 5680361Abstract: Additional modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access.Type: GrantFiled: February 14, 1995Date of Patent: October 21, 1997Assignee: Rambus, Inc.Inventors: Frederick A. Ware, John B. Dillon, Richard M. Barth, Billy Wayne Garrett, Jr., John Girdner Atwood, Jr., Michael P. Farmwald, Richard DeWitt Crisp