Patents by Inventor Bimal Patel
Bimal Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11371850Abstract: Systems, methods, and other embodiments associated with a shortest path engine for warehouse management are described. In one embodiment, a method determines a shortest path between a first location and a second location. The method includes receiving a request for a shortest path between a first location and a second location and accessing a first data structure. The first data structure maps the first location to a first reference point and the second location to a second reference point. A shortest path between the first reference point and the second reference point is determined and the determined shortest path is returned.Type: GrantFiled: October 12, 2020Date of Patent: June 28, 2022Assignee: Oracle International CorporationInventor: Bimal Patel
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Publication number: 20210025719Abstract: Systems, methods, and other embodiments associated with a shortest path engine for warehouse management are described. In one embodiment, a method determines a shortest path between a first location and a second location. The method includes receiving a request for a shortest path between a first location and a second location and accessing a first data structure. The first data structure maps the first location to a first reference point and the second location to a second reference point. A shortest path between the first reference point and the second reference point is determined and the determined shortest path is returned.Type: ApplicationFiled: October 12, 2020Publication date: January 28, 2021Inventor: Bimal PATEL
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Patent number: 10801842Abstract: Systems, methods, and other embodiments associated with a shortest path engine for warehouse management are described. In one embodiment, a method determines a shortest path between a first location and a second location. The method includes receiving a request for a shortest path between a first location and a second location and accessing a first data structure. The first data structure maps the first location to a first reference point and the second location to a second reference point. A shortest path between the first reference point and the second reference point is determined and the determined shortest path is returned.Type: GrantFiled: December 9, 2014Date of Patent: October 13, 2020Assignee: Oracle International CorporationInventor: Bimal Patel
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Patent number: 10719372Abstract: A system for dynamically parallelizing the loading operation for loading a data file onto a database. The dynamic parallelization of the loading operation involves scanning the data file in segments, such that scanning of an individual segment terminates when the scanned information is enough to enable loading of the segment across a plurality of exclusive-access memory blocks. Following the scanning of the first data file segment, the parallelized loading of each scanned segment occurs in a lock-step-mode with the scanning operation. As such, the loading of each scanned data segment is performed in parallel across multiple exclusive-access memory location, as determined by the prior scanning results, and furthermore in parallel with the scanning of a subsequent segment of the data file.Type: GrantFiled: May 22, 2017Date of Patent: July 21, 2020Assignee: Oracle International CorporationInventors: Subrahmanyam Kolachala, Jianwu Xu, Tak Hong, Larry E. Roddenberry, Dengsheng Huang, Mehdi Khosravi, Philip Geoffrey Holland, Bimal Patel, Anoop Mohan, Kiran Kumar Shetty, Weigang Lang, Eric Bloemeke, Zhibin Huang, Scott D. Coulter
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Patent number: 10656964Abstract: A system for generating a parallel calculation plan to evaluate a rule-set or a rule-based expression list by spilling the list of rule-based expressions into multiple task units and reconfiguring all independent task units at the same calculation levels into several parallelized task groups such that task units within each task group may be scheduled for parallel execution across a cluster of processing nodes. The parallelization may be dynamically determined based on generated tasks but may further be subject to an additional layer of parallelization based on range-based splitting of each task into multiple parallel executable subtasks. The final parallelized calculation plan may include a set of sequentially ordered task groups based on logical dependencies and problem partitioning with information regarding parallelized execution of each task group.Type: GrantFiled: May 16, 2017Date of Patent: May 19, 2020Assignee: Oracle International CorporationInventors: Subrahmanyam Kolachala, Jianwu Xu, Tak Hong, Larry E. Roddenberry, Dengsheng Huang, Mehdi Khosravi, Philip Geoffrey Holland, Bimal Patel, Anoop Mohan, Kiran Kumar Shetty, Weigang Lang, Eric Bloemeke, Zhibin Huang, Scott D. Coulter
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Publication number: 20180336062Abstract: A system for generating a parallel calculation plan to evaluate a rule-set or a rule-based expression list by spilling the list of rule-based expressions into multiple task units and reconfiguring all independent task units at the same calculation levels into several parallelized task groups such that task units within each task group may be scheduled for parallel execution across a cluster of processing nodes. The parallelization may be dynamically determined based on generated tasks but may further be subject to an additional layer of parallelization based on range-based splitting of each task into multiple parallel executable subtasks. The final parallelized calculation plan may include a set of sequentially ordered task groups based on logical dependencies and problem partitioning with information regarding parallelized execution of each task group.Type: ApplicationFiled: May 16, 2017Publication date: November 22, 2018Inventors: Subrahmanyam KOLACHALA, Jianwu XU, Tak HONG, Larry E. RODDENBERRY, Dengsheng HUANG, Mehdi KHOSRAVI, Philip Geoffrey HOLLAND, Bimal PATEL, Anoop MOHAN, Kiran Kumar SHETTY, Weigang LANG, Eric BLOEMEKE, Zhibin HUANG, Scott D. COULTER
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Publication number: 20180336073Abstract: A system for dynamically parallelizing the loading operation for loading a data file onto a database. The dynamic parallelization of the loading operation involves scanning the data file in segments, such that scanning of an individual segment terminates when the scanned information is enough to enable loading of the segment across a plurality of exclusive-access memory blocks. Following the scanning of the first data file segment, the parallelized loading of each scanned segment occurs in a lock-step-mode with the scanning operation. As such, the loading of each scanned data segment is performed in parallel across multiple exclusive-access memory location, as determined by the prior scanning results, and furthermore in parallel with the scanning of a subsequent segment of the data file.Type: ApplicationFiled: May 22, 2017Publication date: November 22, 2018Inventors: Subrahmanyam KOLACHALA, Jianwu XU, Tak HONG, Larry E. RODDENBERRY, Dengsheng HUANG, Mehdi KHOSRAVI, Philip Geoffrey HOLLAND, Bimal PATEL, Anoop MOHAN, Kiran Kumar SHETTY, Weigang LANG, Eric BLOEMEKE, Zhibin HUANG, Scott D. COULTER
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Publication number: 20160161263Abstract: Systems, methods, and other embodiments associated with a shortest path engine for warehouse management are described. In one embodiment, a method determines a shortest path between a first location and a second location. The method includes receiving a request for a shortest path between a first location and a second location and accessing a first data structure. The first data structure maps the first location to a first reference point and the second location to a second reference point. A shortest path between the first reference point and the second reference point is determined and the determined shortest path is returned.Type: ApplicationFiled: December 9, 2014Publication date: June 9, 2016Inventor: Bimal PATEL
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Publication number: 20070201545Abstract: Systems and method for controlling the gain of an equalizer are provided. In these systems and methods, bit errors in a serial data stream received by an equalizer are detected, and the gain of the equalizer is set in response to the detected bit errors in the serial data stream.Type: ApplicationFiled: January 3, 2007Publication date: August 30, 2007Inventors: Eliyahu Zamir, Bimal Patel, Mathew Johnson, Mohammad Shakiba
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Publication number: 20070129482Abstract: Disclosed are resinous compositions comprising a colorant combination comprising at least one inorganic infrared reflecting pigment and at least one organic colorant, wherein the combination of inorganic pigment and organic colorant results in a molded part with an L* value of less than about 30 with specular component included, and a heating build-up (HBU) as measured according to ASTM D4803-89 of less than about 34° C. A method to make such compositions is also an embodiment of the invention as are articles made from such compositions.Type: ApplicationFiled: November 21, 2006Publication date: June 7, 2007Inventors: Olga Kuvshinnikova, Nela Stafie, Bimal Patel
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Patent number: 7133913Abstract: The invention is an improved method and apparatus for information routing and sharing in multiple computer networks, which can facilitate automatic integration of diverse network and data systems. In an integrated data network comprising multiple computer systems, distinct information users and sources may each be considered as a block. An information routing layer coupled to each of the blocks provides for the routing of information provided in the form of datasets, which are combinations of field names, types, values and other components. An existing dataset can be provided or an aggregate set can be constructed as required to meet an information request from a block in the integrated data network without programmatic or specified workflow reference to other blocks.Type: GrantFiled: August 9, 2001Date of Patent: November 7, 2006Inventors: Jacoby M. Thwaites, Bimal Patel
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Publication number: 20050277710Abstract: One embodiment of a tagged resin comprises: a thermoplastic material and a marked particle. The marked particle comprises a covert identifier, and the particle has an aspect ratio of about 1:1 to about 10:1. One embodiment of the method for making a tagged item comprises: processing a thermoplastic material and a marked particle comprising a covert identifier, to form a processed item. The processing is selected from the group consisting of extruding, injection-molding, masterbatching, masterblending, thermoforming, blow-molding, and combinations comprising at least one of the foregoing processing. The marked particles in the processed item comprise an aspect ratio of about 1:1 to about 10:1.Type: ApplicationFiled: June 14, 2004Publication date: December 15, 2005Inventors: Richard Joyce, Bimal Patel, Philippe Schottland
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Publication number: 20050193142Abstract: The invention provides an improved method and apparatus for information routing and sharing in multiple computer networks, which can facilitate automatic integration of diverse network and data systems. In an integrated data network comprising multiple computer systems, distinct information users and sources are treated as “Blocks” 1. An information Routing Layer 3 coupled to the Blocks provides for the routing of information stored in the form of Datasets, which are sets of field names, types, values and other components, from one Block 1 to another by a process of “Information Routing”, such that an Aggregate Route can be constructed as required to meet a request from a Block in the integrated data network without programmatic or specified workflow reference to other Blocks using one or more available Datasets and novel Functions to supply and process information as required.Type: ApplicationFiled: February 7, 2003Publication date: September 1, 2005Inventors: Jacoby Thwaites, Bimal Patel
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Patent number: 6584484Abstract: An n-bit carry-skip adder includes a number of carry-skip stages and a logic circuit associated with one or more of the stages. The logic circuit includes split-adder logic and carry-skip logic configured such that a split control signal associated with the split-adder logic is applied to at least one gate of the carry-skip logic, so as to reduce a carry propagation delay of the adder. In an illustrative embodiment, the logic circuit is associated with an (n/2+1)th carry-skip stage of the adder, and the adder is configured to perform two parallel n/2-bit additions when the split control signal is at a first logic level, and to perform a single n-bit addition when the split control signal is at a second logic level. Advantageously, the invention allows the split-adder logic to be incorporated in a manner which minimizes the carry propagation delay without increasing the required circuit area.Type: GrantFiled: May 11, 2000Date of Patent: June 24, 2003Assignee: Agere Systems Inc.Inventors: Alexander Goldovsky, Bimal Patel