Patents by Inventor Bimal Poddar

Bimal Poddar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11704167
    Abstract: Approaches in accordance with various embodiments can reduce scheduling delays due to concurrent processing requests, as may involve VSyncs in multi-streaming systems. The software synchronization signals can be staggered relative to each other by offsetting an initial synchronization signal. These software synchronization signals can be readjusted over time such that each synchronization signal maintains the same relative offset, as may be with respect to other applications or containers.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: July 18, 2023
    Assignee: Nvidia Corporation
    Inventors: Bimal Poddar, Donghan Ryu, Michael Gold, Samuel Reed Koser, Xiao Bo Zhao Zhang
  • Publication number: 20230084849
    Abstract: Approaches in accordance with various embodiments can reduce scheduling delays due to concurrent processing requests, as may involve VSyncs in multi-streaming systems. The software synchronization signals can be staggered relative to each other by offsetting an initial synchronization signal. These software synchronization signals can be readjusted over time such that each synchronization signal maintains the same relative offset, as may be with respect to other applications or containers.
    Type: Application
    Filed: August 15, 2022
    Publication date: March 16, 2023
    Inventors: Bimal Poddar, Donghan Ryu, Michael Gold, Samuel Reed Koser, Xiao Bo Zhao Zhang
  • Patent number: 11416311
    Abstract: Approaches in accordance with various embodiments can reduce scheduling delays due to concurrent processing requests, as may involve VSyncs in multi-streaming systems. The software synchronization signals can be staggered relative to each other by offsetting an initial synchronization signal. These software synchronization signals can be readjusted over time such that each synchronization signal maintains the same relative offset, as may be with respect to other applications or containers.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: August 16, 2022
    Assignee: NVIDIA CORPORATION
    Inventors: Bimal Poddar, Donghan Ryu, Michael Gold, Samuel Reed Koser, Xiao Bo Zhao Zhang
  • Publication number: 20210240546
    Abstract: Approaches in accordance with various embodiments can reduce scheduling delays due to concurrent processing requests, as may involve VSyncs in multi-streaming systems. The software synchronization signals can be staggered relative to each other by offsetting an initial synchronization signal. These software synchronization signals can be readjusted over time such that each synchronization signal maintains the same relative offset, as may be with respect to other applications or containers.
    Type: Application
    Filed: November 5, 2020
    Publication date: August 5, 2021
    Inventors: Bimal Poddar, Donghan Ryu, Michael Gold, Samuel Reed Koser, Xiao Bo Zhao Zhang
  • Patent number: 10403024
    Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 3, 2019
    Assignee: INTEL CORPORATION
    Inventors: Bimal Poddar, Prasoonkumar Surti, Rahul P. Sathe
  • Patent number: 10297046
    Abstract: Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventor: Bimal Poddar
  • Publication number: 20180268597
    Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.
    Type: Application
    Filed: May 24, 2018
    Publication date: September 20, 2018
    Inventors: Bimal Poddar, Prasoonkumar Surti, Rahul P. Sathe
  • Patent number: 9984490
    Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: May 29, 2018
    Assignee: INTEL CORPORATION
    Inventors: Bimal Poddar, Prasoonkumar Surti, Rahul P. Sathe
  • Patent number: 9916682
    Abstract: The power consumption of processor-based devices may be reduced by reducing the consumption of power during graphics processing. In some embodiments, the precision of pixel shading in parts of images where artifacts are less objectionable may be reduced. For example, in areas the user is not directly looking at, precision may be reduced to save power. At the same time, because a person is not focusing on those regions, even if usually perceptible artifacts occur because of the reduced precision, an overall pleasing depiction may be achieved.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: March 13, 2018
    Assignee: Intel Corporation
    Inventors: Rahul P. Sathe, Bimal Poddar, Jon N. Hasselgren
  • Patent number: 9824412
    Abstract: In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Saurabh Sharma, Subramaniam Maiyuran, Thomas A. Piazza, Kalyan K. Bhiravabhatla, Peter L. Doyle, Paul A. Johnson, Bimal Poddar, Jon N. Hasselgren, Carl J. Munkberg, Tomas G. Akenine-Moller, Harri Syrja, Kevin Rogovin, Robert L. Farrell
  • Publication number: 20170330371
    Abstract: A mechanism is described for facilitating dynamic culling of composite objects producing not visible change in graphics images on computing devices. A method of embodiments, as described herein, includes identifying one or more objects of a plurality of objects of a frame for being potentially insignificant to be included in a subsequent frame, and applying one or more bounding boxes encompassing the one or more objects. The method may further include determining, basing on a vertex transformation, one or more minimum bounding rectangles corresponding to the one or more bounding boxes. The method may further include determining, based on rasterization rules, coverage of the one or more minimum bounding rectangles to one or more pixel centers of one or more pixels, and selecting a first object of the one or more objects to be included in the subsequent frame, if a first of the one or more corresponding minimum bounding rectangles touch or include a pixel center of a pixel.
    Type: Application
    Filed: December 23, 2014
    Publication date: November 16, 2017
    Inventors: JACEK KROL, BIMAL PODDAR, TOMASZ PONIECKI
  • Patent number: 9741154
    Abstract: According to some embodiments of the present invention, pixel throughput may be improved by performing depth tests and recording the results on the granularity of an input geometry object. An input geometry object is any object within the depiction represented by a primitive, such as a triangle within an input triangle list or a patch within an input patch list.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Thomas A. Piazza, Bimal Poddar, Peter L. Doyle
  • Publication number: 20170228893
    Abstract: Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed.
    Type: Application
    Filed: September 19, 2016
    Publication date: August 10, 2017
    Applicant: Intel Corporation
    Inventor: Bimal Poddar
  • Publication number: 20170124757
    Abstract: The power consumption of processor-based devices may be reduced by reducing the consumption of power during graphics processing. In some embodiments, the precision of pixel shading in parts of images where artifacts are less objectionable may be reduced. For example, in areas the user is not directly looking at, precision may be reduced to save power. At the same time, because a person is not focusing on those regions, even if usually perceptible artifacts occur because of the reduced precision, an overall pleasing depiction may be achieved.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 4, 2017
    Inventors: Rahul P. Sathe, Bimal Poddar, Jon N. Hasselgren
  • Patent number: 9601092
    Abstract: The introduction of an “out-of-memory” marker in the sorted tile geometry sequence for a tile may aid in handling out-of-memory frames. This marker allows hardware to continue rendering using the original data stream instead of the sorted data stream. This enables use of the original data stream allows the system to continue rendering without requiring any driver intervention. During the visibility generation/sorting phase, the number of memory pages required for storing the data for a rendering pass is continuously tracked. This tracking includes tracking the pages that are required even if the hardware had not run out-of-memory. This information can be monitored by a graphics driver and the driver can provide more memory pages for the system to work at full efficiency.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Michael Apodaca, Thomas A. Piazza, Bimal Poddar
  • Patent number: 9589312
    Abstract: A mechanism is described for dynamically optimizing color buffer clear performance in graphics processing units. A method of embodiments, as described herein, includes allocating and initializing a first set of control bits associated with a framebuffer in a graphics processing unit (GPU), and rendering a first frame, wherein the first set of control bits are associated with the first frame. The method may further include allocating a second set of control bits associated with a second frame, and rendering the second frame. The method may further include facilitating an expedited resolve operation of the second frame based on a frame-to-frame coherence associated with the first and second frames.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: March 7, 2017
    Assignee: Intel Corporation
    Inventor: Bimal Poddar
  • Publication number: 20160364898
    Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.
    Type: Application
    Filed: June 11, 2015
    Publication date: December 15, 2016
    Inventors: Bimal Poddar, Prasoonkumar Surti, Rahul P. Sathe
  • Publication number: 20160275920
    Abstract: The introduction of an “out-of-memory” marker in the sorted tile geometry sequence for a tile may aid in handling out-of-memory frames. This marker allows hardware to continue rendering using the original data stream instead of the sorted data stream. This enables use of the original data stream allows the system to continue rendering without requiring any driver intervention. During the visibility generation/sorting phase, the number of memory pages required for storing the data for a rendering pass is continuously tracked. This tracking includes tracking the pages that are required even if the hardware had not run out-of-memory. This information can be monitored by a graphics driver and the driver can provide more memory pages for the system to work at full efficiency.
    Type: Application
    Filed: March 19, 2015
    Publication date: September 22, 2016
    Inventors: Michael Apodaca, Thomas A. Piazza, Bimal Poddar
  • Patent number: 9449362
    Abstract: Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: September 20, 2016
    Assignee: INTEL CORPORATION
    Inventor: Bimal Poddar
  • Patent number: 9390463
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine color information for multiple graphical layers of a graphical display at a location of a pixel, and to determine a pixel color information for the pixel at the location based on the color information for each of the multiple graphical layers.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: July 12, 2016
    Assignee: INTEL CORPORATION
    Inventor: Bimal Poddar