Abstract: A re-timer device includes transceiver circuitry. The transceiver circuitry includes clock generation circuitry and first receiver circuitry. The clock generation circuitry generates a first clock signal. The first receiver circuitry receives the first clock signal and a first input signal. The first receiver circuitry generates a first frequency offset value based on the first input signal and the first clock signal. The first input signal has a first frequency and the first clock signal has a second frequency different than the first frequency. The first receiver circuitry outputs the first frequency offset value.

Abstract: A voltage controlled oscillator (VCO) circuitry includes a varactor array. The varactor array includes a first varactor unit including a first varactor, a second varactor, and first switch circuitry. The first varactor is connected to a first node and a second node, and the second varactor is connected to the second node and a third node. The second node receives a voltage control signal. The first switch circuitry is electrically coupled to the first node and the third node, and selectively electrically couples a first voltage signal to the first node and the third node based on a first control signal.

Abstract: A voltage controlled oscillator (VCO) circuitry includes a varactor array. The varactor array includes a first varactor unit including a first varactor, a second varactor, and first switch circuitry. The first varactor is connected to a first node and a second node, and the second varactor is connected to the second node and a third node. The second node receives a voltage control signal. The first switch circuitry is electrically coupled to the first node and the third node, and selectively electrically couples a first voltage signal to the first node and the third node based on a first control signal.

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

Abstract: A system for clock calibration is described herein which comprises a serializer configured to convert an input data stream in parallel format to provide an out data stream in a serial format; a clock source configured to generate one or more clock signals; a first frequency divider configured to provide at least one divided clock signal of the one or more clock signals; a delay line configured to delay at least one divided clock signal; and a clock calibrator configured to control delay of the at least one divided clock signal at the delay line to adjust the one or more divided clock signals at a fixed relationship with respect to the one or more clock signals based on voltage and temperature variation.

Abstract: A clock generation and correction (CGC) circuit comprises a clock and data recovery (CDR) circuit, a start-of-frame (SOF) detector circuit, a counter, a digital logic circuit, a fractional-N phase locked loop (PLL), and an oscillator circuit. The CDR receives an input data signal and an internal clock signal and generates a recovered data signal. The SOF detector circuit generates a toggle signal based on a comparison of the recovered data signal to a predetermined data signal pattern. The counter generates a clock cycle count signal based on the toggle signal. The digital logic circuit generates a frequency adjustment signal based on an error in the frequency of the clock signal. The oscillator circuit generates an intermediate clock signal. The fractional-N PLL circuit receives the frequency adjustment signal and the intermediate clock signal and modifies the internal clock signal based on the frequency adjustment signal.

Abstract: A clock generation and correction (CGC) circuit comprises a clock and data recovery (CDR) circuit, a start-of-frame (SOF) detector circuit, a counter, a digital logic circuit, a fractional-N phase locked loop (PLL), and an oscillator circuit. The CDR receives an input data signal and an internal clock signal and generates a recovered data signal. The SOF detector circuit generates a toggle signal based on a comparison of the recovered data signal to a predetermined data signal pattern. The counter generates a clock cycle count signal based on the toggle signal. The digital logic circuit generates a frequency adjustment signal based on an error in the frequency of the clock signal. The oscillator circuit generates an intermediate clock signal. The fractional-N PLL circuit receives the frequency adjustment signal and the intermediate clock signal and modifies the internal clock signal based on the frequency adjustment signal.

Abstract: A phase-locked loop (PLL) for generating a VCO output signal at a target frequency has been disclosed. The PLL includes at least first and second VCOs, first and second multiplexers, and a frequency divider. The first and second VCOs generate first and second output signals over first and second frequency ranges, respectively. The first multiplexer receives the first and second output signals from the first and second VCOs, respectively, and outputs the first output signal when the target frequency is in the first frequency range and the second output signal when the target frequency is in the second frequency range or less than the first frequency range. The frequency divider divides a frequency of the second output signal by a division factor to generate a third output signal. The second multiplexer outputs one of the first, second, and third output signals as the VCO output signal.

Abstract: A clock and data recovery (CDR) circuit includes first through ninth samplers, a clock recovery circuit, a level finding circuit, an offset voltage generator, and a data recovery circuit. Each of the first through ninth samplers samples a data signal based on one of first through ninth reference offset voltage levels to generate first through ninth intermediate signals, respectively. The clock recovery circuit generates the first through fourth clock signals based on the first, second, fifth, and eighth intermediate signals. The level finding circuit generates a band level signal by varying the third intermediate signal. The offset voltage generator generates one of: the fourth and seventh reference offset voltage levels, the fifth and eighth reference offset voltage levels, and the sixth and ninth reference offset voltage levels based on the band level signal. The data recovery circuit detects an output data signal based on the fourth through ninth intermediate signals.

Abstract: A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an up-down counter. The BBPD generates an early-late signal by determining whether serialized data received by the BBPD is early or late with respect to a VCO clock signal generated by the VCO. A phase of the VCO clock signal is controlled based on the early-late signal. The frequency control circuit compares a frequency of the VCO clock signal and a target frequency and generates an up/down signal. Based on the up/down signal, the up-down counter increments or decrements the frequency of the VCO clock signal to match the target frequency.

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

Abstract: A system for clock calibration is described herein which comprises a serializer configured to convert an input data stream in parallel format to provide an out data stream in a serial format; a clock source configured to generate one or more clock signals; a first frequency divider configured to provide at least one divided clock signal of the one or more clock signals; a delay line configured to delay at least one divided clock signal; and a clock calibrator configured to control delay of the at least one divided clock signal at the delay line to adjust the one or more divided clock signals at a fixed relationship with respect to the one or more clock signals based on voltage and temperature variation.

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

Abstract: A clock and data recovery (CDR) circuit receives a data signal and generates a clock signal and a recovered data signal. The CDR circuit includes a clock-recovery circuit (CRC), a sampling phase-recovery circuit (PRC), an analog-to-digital converter (ADC), and a data-recovery circuit (DRC). The CRC receives the data signal and generates an intermediate clock signal. The PRC receives the intermediate clock signal, a sampled data signal and the recovered data signal, and generates the clock signal. The ADC receives the data signal and generates the sampled data signal. The DRC receives the sampled data signal and generates the recovered data signal. The clock signal is phase and frequency synchronized with the data signal.

Abstract: A clock and data recovery (CDR) circuit receives a data signal and generates a clock signal and a recovered data signal. The CDR circuit includes a clock-recovery circuit (CRC), a sampling phase-recovery circuit (PRC), an analog-to-digital converter (ADC), and a data-recovery circuit (DRC). The CRC receives the data signal and generates an intermediate clock signal. The PRC receives the intermediate clock signal, a sampled data signal and the recovered data signal, and generates the clock signal. The ADC receives the data signal and generates the sampled data signal. The DRC receives the sampled data signal and generates the recovered data signal. The clock signal is phase and frequency synchronized with the data signal.

Abstract: A clock and data recovery (CDR) circuit for data sampling includes a sampler, a phase detector, a proportional-integral (PI) controller, and an oscillator. The sampler receives a data signal and a clock signal, and generates first, second, and third sampled signals. The phase detector receives the first, second, and third sampled signals, and generates first and second early-late vote (ELV) signals. The charge pump steers a current signal into or out of one of summing nodes based on the first and second ELV signals. The integrator circuit receives the current signal from one of the summing nodes, and generates a first control signal. The proportional circuit receives the first and second ELV signals, and generates a second control signal. The oscillator receives the first and second control signals from the integrator and proportional circuits, respectively, and generates a clock signal for sampling the data.

Abstract: A clock and data recovery (CDR) circuit for data sampling includes a sampler, a phase detector, a proportional-integral (PI) controller, and an oscillator. The sampler receives a data signal and a clock signal, and generates first, second, and third sampled signals. The phase detector receives the first, second, and third sampled signals, and generates first and second early-late vote (ELV) signals. The charge pump steers a current signal into or out of one of summing nodes based on the first and second ELV signals. The integrator circuit receives the current signal from one of the summing nodes, and generates a first control signal. The proportional circuit receives the first and second ELV signals, and generates a second control signal. The oscillator receives the first and second control signals from the integrator and proportional circuits, respectively, and generates a clock signal for sampling the data.

Abstract: A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an up-down counter. The BBPD generates an early-late signal by determining whether serialized data received by the BBPD is early or late with respect to a VCO clock signal generated by the VCO. A phase of the VCO clock signal is controlled based on the early-late signal. The frequency control circuit compares a frequency of the VCO clock signal and a target frequency and generates an up/down signal. Based on the up/down signal, the up-down counter increments or decrements the frequency of the VCO clock signal to match the target frequency.

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

Abstract: A lock time measurement system to determine a lock time includes a measurement device, a serializer-deserializer (SERDES), a pattern generator, and a splitter. In a first mode, the SERDES receives first data from the pattern generator by way of the splitter. A receiver of the SERDES outputs a recovered clock signal based on the first data to a transmitter. The transmitter includes a serializer and a multiplexer. The serializer receives the recovered clock signal by way of the multiplexer and modifies second data based on the recovered clock signal and outputs serial data. A measurement device, connected to the transmitter and the splitter determines the lock time. In a second mode, the SERDES functions as a transmitter for transmitting data and a receiver for receiving data in a communication link. The system has a better accuracy and utilizes existing receiver and driver circuits.