Abstract: An automatic-gain control circuit includes a variable-gain amplifier, a peak-detecting circuit, and an adjustable charge/discharge circuit. The variable-gain amplifier receives an input signal and adjusts the input signal based on a gain-factor control signal for generating a corresponding output signal. The peak-detecting circuit is coupled to the variable-gain amplifier for generating a comparing signal according to a reference signal and the output signal. The adjustable charge/discharge circuit is coupled to the peak-detecting circuit and the variable-gain amplifier for outputting a charge current or a discharge current based on the comparing signal, thereby generating the gain-factor control signal. The ratio between the charge current and the discharge current is adjustable.

Abstract: A cyclic pipeline analog to digital converter includes a dual mode sample and hold circuit, a multiplying digital to analog converter (MDAC), a sub-analog to digital converter (sub-ADC) and a decoder. The dual mode sample and hold circuit has a charge-redistribution mode and a flip-around mode. The dual mode sample and hold circuit receives first and second input voltages and first and second feedback voltages and generates a differential output signal pair. The MDAC receives the differential output signal pair and a digital multiplying word and generates the first and second feedback voltages. The sub-ADC receives the differential output signal pair and generates the digital multiplying word and a digital output word. The decoder converts the digital output word to a digital output corresponding to the first and second input voltages.

Abstract: An LGA socket (1) includes an insulative housing (2) and a plurality of conductive contacts (3) received in the housing. The housing defines a recessed area (25) surrounded by a number of sidewalls (21). The contacts are received in the recessed area. Each of the sidewall defines a plurality of slots (27) and a plurality of corresponding shielding terminals (4) fastened in the slots. Each shielding terminal includes a fastening portion (41), a linking portion (43) extending from the fastening portion, a first contacting arm (421) extending from one end of the linking portion, and a second contacting arm (422) extending form the other end of the linking portion. The first and second contacting arms dispose out of the sots for elastically connecting with external components.

Abstract: An LGA socket (1) includes an insulative housing (2) and a plurality of conductive contacts (3) received in the housing. The housing defines a recessed area (25) surrounded by a number of sidewalls (21). The contacts are received in the recessed area. Each of the sidewall defines a plurality of slots (27) and a plurality of corresponding shielding terminals (4) fastened in the slots. Each shielding terminal includes a fastening portion (41), a linking portion (43) extending from the fastening portion, a first contacting arm (421) extending from one end of the linking portion, and a second contacting arm (422) extending form the other end of the linking portion. The first and second contacting arms dispose out of the sots for elastically connecting with external components.

Abstract: A cyclic pipeline analog to digital converter includes a dual mode sample and hold circuit, a multiplying digital to analog converter (MDAC), a sub-analog to digital converter (sub-ADC) and a decoder. The dual mode sample and hold circuit has a charge-redistribution mode and a flip-around mode. The dual mode sample and hold circuit receives first and second input voltages and first and second feedback voltages and generates a differential output signal pair. The MDAC receives the differential output signal pair and a digital multiplying word and generates the first and second feedback voltages. The sub-ADC receives the differential output signal pair and generates the digital multiplying word and a digital output word. The decoder converts the digital output word to a digital output corresponding to the first and second input voltages.

Abstract: According to an embodiment of the present invention, an LGA connector (10) for forming electrical connection between an LGA package and a circuit substrate includes a dielectric housing (20) defining a number of passages (2024) and a number of conductive terminals (30) seated in the corresponding passages, respectively. The dielectric housing is provided with a number of reinforced columns (2026) capable of being inserted into a number of recesses correspondingly defined in the circuit substrate, to favorably prevent the dielectric housing from being displaced relative to the circuit substrate.

Abstract: Transconductance filter circuits. A transconductor includes two inputs for receiving two differential voltages, and a first output terminal and a second output terminal for outputting two differential signals. A first capacitor array includes at least one first switch capacitor unit controlled by a first signal, and a first equivalent capacitor coupled between the first output terminal and the second output terminal when the first signal is enabled. two second capacitor arrays each includes at least one second switch capacitor unit controlled by a second signal, two second equivalent capacitors respectively coupled between the first output terminal and a ground level, and between the second output terminal and the ground level when the second signal is enabled. The capacitance of the first equivalent capacitor exceeds that of the two second equivalent capacitors connected in serial.

Abstract: An LGA socket (1) includes an insulative housing (2) and a plurality of conductive contacts (3) received in the housing. The housing defines a recessed area (25) surrounded by a number of sidewalls (21). The contacts are received in the recessed area. Each of the sidewall defines a plurality of slots (27) and a plurality of corresponding shielding terminals (4) fastened in the slots. Each shielding terminal includes a fastening portion (41), a linking portion (43) extending from the fastening portion, a first contacting arm (421) extending from one end of the linking portion, and a second contacting arm (422) extending form the other end of the linking portion. The first and second contacting arms dispose out of the sots for elastically connecting with external components.

Abstract: According to an embodiment of the present invention, an LGA connector (10) for forming electrical connection between an LGA package and a circuit substrate includes a dielectric housing (20) defining a number of passages (2024) and a number of conductive terminals (30) seated in the corresponding passages, respectively. The dielectric housing is provided with a number of reinforced columns (2026) capable of being inserted into a number of recesses correspondingly defined in the circuit substrate, to favorably prevent the dielectric housing from being displaced relative to the circuit substrate.

Abstract: A clock recovery circuit for generating an output signal that is synchronized with an input signal. The clock recovery circuit includes a charge pump, a first filter, an oscillator, a switch circuit, and a second filter. When the charge pump operates, the switch circuit will disconnect the first filter from the oscillator. Additionally, when the charge pump stops operating, the switch circuit will connect the first filter and the oscillator such that the oscillator adjusts a frequency or phase of the output signal according to the output voltage of the first filter.

Abstract: Transconductance filter circuits. A transconductor includes two inputs for receiving two differential voltages, and a first output terminal and a second output terminal for outputting two differential signals. A first capacitor array includes at least one first switch capacitor unit controlled by a first signal, and a first equivalent capacitor coupled between the first output terminal and the second output terminal when the first signal is enabled. two second capacitor arrays each includes at least one second switch capacitor unit controlled by a second signal, two second equivalent capacitors respectively coupled between the first output terminal and a ground level, and between the second output terminal and the ground level when the second signal is enabled. The capacitance of the first equivalent capacitor exceeds that of the two second equivalent capacitors connected in serial.

Abstract: A phase locked loop circuit includes a loop filter having a first input terminal and a second input terminal and including a first capacitor coupled to the first terminal; a resistor having one terminal coupled to the first input terminal; a second capacitor coupled to the second input terminal; and a source follower having an input terminal coupled to the second input terminal and an output terminal coupled the other terminal of the resistor; a first charge pump coupled to the first input terminal outputting a first current; and a second charge pump coupled to the second input terminal outputting a second current; wherein the first current is a multiple of the second current.

Abstract: A photomask includes a substrate having a transparent substrate, a mask pattern positioned on a surface of the transparent substrate, a transparent electrostatic discharge (ESD) ring positioned on the surface of the transparent substrate and surrounding the mask pattern, a pellicle covering over the mask pattern, and a mounting adhesive used for sticking the pellicle on the transparent electrostatic discharge ring. The transparent electrostatic discharge ring is utilized to examine a binding condition between the pellicle and the transparent substrate and to suppress an electrostatic discharge.

Abstract: A duty cycle correction method converts a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction method processes the pair of differential analog signals into a first digital pulse signal and a second digital pulse signal, wherein the first digital pulse signal and the second digital pulse signal have a specified phase difference therebetween, frequency-divides the first digital pulse signal and the second digital pulse signal into a third digital pulse signal and a fourth digital pulse signal, and generates the output pulse signal according to the third and fourth digital pulse signals. The output pulse signal can be generated by performing an exclusive OR operation of the third and fourth digital pulse signals.

Abstract: A signal processing circuit for adjusting an input signal and generating a corresponding digital output signal in an optical disk driver is provided. The signal processing circuit includes an attenuator for receiving and attenuating the input signal and then generating an attenuated output signal; a gain controllable amplifier for receiving and amplifying the input signal and then generating an amplified output signal; a control unit providing a control signal and a select signal, the control signal is directed to the attenuator and the gain controllable amplifier for enabling/disabling the attenuator and the gain controllable amplifier and for controlling their gains such that one of the attenuator and gain controllable amplifier is enabled at a time; and a waveform adjuster circuit for adjusting the amplified/attenuated output signal delivered from the gain controllable amplifier or the attenuator so as to generate the digital signal related to the input signal.

Abstract: A duty cycle correction method converts a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction method processes the pair of differential analog signals into a first digital pulse signal and a second digital pulse signal, wherein the first digital pulse signal and the second digital pulse signal have a specified phase difference therebetween, frequency-divides the first digital pulse signal and the second digital pulse signal into a third digital pulse signal and a fourth digital pulse signal, and generates the output pulse signal according to the third and fourth digital pulse signals. The output pulse signal can be generated by performing an exclusive OR operation of the third and fourth digital pulse signals.

Abstract: A duty cycle correction circuit is provided for converting a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction circuit includes a first differential-to-single-ended buffer circuit, a second differential-to-single-ended buffer circuit, a first frequency divider, a second frequency divider and a symmetrical exclusive OR element. The first and the second differential-to-single-ended buffer circuits are used for processing the pair of differential analog signals into a first and a second digital pulse signals, respectively. The first and the second frequency dividers are employed for frequency-dividing the first and the digital pulse signal into a third and a fourth digital pulse signal, respectively. The symmetrical exclusive OR element is used for performing an exclusive OR operation so as to produce the output pulse signal.

Abstract: A duty cycle correction circuit is provided for converting a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction circuit includes a first differential-to-single-ended buffer circuit, a second differential-to-single-ended buffer circuit, a first frequency divider, a second frequency divider and a symmetrical exclusive OR element. The first and the second differential-to-single-ended buffer circuits are used for processing the pair of differential analog signals into a first and a second digital pulse signals, respectively. The first and the second frequency dividers are employed for frequency-dividing the first and the digital pulse signal into a third and a fourth digital pulse signal, respectively. The symmetrical exclusive OR element is used for performing an exclusive OR operation so as to produce the output pulse signal.

Abstract: A signal processing circuit and related method for adjusting an input signal and generating a corresponding output signal in an optical disk driver. The signal processing circuit includes an attenuator, an amplifier, a controller, and a waveform adjuster. The attenuator reduces the input signal and generates a first temporary output signal. The amplifier enlarges the input signal and generates a second temporary output signal. The controller selectively enables one of the amplifier or the attenuator according to the first and second temporary signals. The waveform adjuster receives the temporary output signals and generates the output signals.

Abstract: The present invention provides a data recovery circuit for generating an output signal that is synchronized with an input signal. The data recovery circuit includes a charge pump, a first filter, an oscillator, a switch circuit, and a second filter. When the charge pump operates, the switch circuit will disconnect the first filter from the oscillator. Additionally, when the charge pump stops operating, the switch circuit will connect the first filter and the oscillator such that the oscillator adjusts a frequency or phase of the output signal according to the output voltage of the first filter.