Patents by Inventor Binfan Liu
Binfan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11108830Abstract: In some aspects, the disclosure is directed to methods and systems for providing coordinative security among network devices across multi-level networks. Shared cryptographic secrets among the network devices are used as the basis for mutual security authentication and peering among these devices. The cryptographic secrets can be embedded in the SoC devices for these devices or dynamically generated based on unique identification information and attributes of these SoC devices. The messages for authentication and peering can be communicated directly among the network devices or indirectly via a cloud security portal entity that acts as a messaging proxy. The mutual authentication and peering process can be carried out coordinately among the network devices and a cloud security portal in a one-to-one mesh relationship, or in a transitive layering relationship, where each network entity authenticates and peers with its direct subordinates in a multi-level network.Type: GrantFiled: July 30, 2018Date of Patent: August 31, 2021Assignee: Avago Technologies International Sales Pte. LimitedInventors: Yong Li, Xuemin Chen, Weimin Zhang, Victor Liang, Binfan Liu
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Publication number: 20190289038Abstract: In some aspects, the disclosure is directed to methods and systems for providing coordinative security among network devices across multi-level networks. Shared cryptographic secrets among the network devices are used as the basis for mutual security authentication and peering among these devices. The cryptographic secrets can be embedded in the SoC devices for these devices or dynamically generated based on unique identification information and attributes of these SoC devices. The messages for authentication and peering can be communicated directly among the network devices or indirectly via a cloud security portal entity that acts as a messaging proxy. The mutual authentication and peering process can be carried out coordinately among the network devices and a cloud security portal in a one-to-one mesh relationship, or in a transitive layering relationship, where each network entity authenticates and peers with its direct subordinates in a multi-level network.Type: ApplicationFiled: July 30, 2018Publication date: September 19, 2019Applicant: Avago Technologies General IP (Singapore) Pte. .Ltd.Inventors: Yong LI, Xuemin CHEN, Weimin ZHANG, Victor LIANG, Binfan LIU
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Patent number: 9729905Abstract: The present disclosure is directed to a system and method for creating overlapping bonded groups of downstream channels that can provide increased channel capacity to improve packing densities, while at the same time limiting complexity and cost increases of new receivers and allowing the continued operation of legacy receivers.Type: GrantFiled: July 29, 2015Date of Patent: August 8, 2017Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Weimin Zhang, Binfan Liu
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Publication number: 20170034544Abstract: The present disclosure is directed to a system and method for creating overlapping bonded groups of downstream channels that can provide increased channel capacity to improve packing densities, while at the same time limiting complexity and cost increases of new receivers and allowing the continued operation of legacy receivers.Type: ApplicationFiled: July 29, 2015Publication date: February 2, 2017Applicant: Broadcom CorporationInventors: Weimin ZHANG, Binfan Liu
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Patent number: 9093134Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.Type: GrantFiled: December 21, 2012Date of Patent: July 28, 2015Assignee: Broadcom CorporationInventors: Binfan Liu, Junyi Xu
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Patent number: 8873647Abstract: Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.Type: GrantFiled: February 14, 2013Date of Patent: October 28, 2014Assignee: Broadcom CorporationInventors: Binfan Liu, Junyi Xu, Weimin Zhang
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Patent number: 8401092Abstract: Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.Type: GrantFiled: July 30, 2010Date of Patent: March 19, 2013Assignee: Broadlogic Network Technologies Inc.Inventors: Binfan Liu, Junyi Xu, Weimin Zhang
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Patent number: 8352834Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.Type: GrantFiled: January 5, 2010Date of Patent: January 8, 2013Assignee: BroadLogic Network Technologies Inc.Inventors: Binfan Liu, Junyi Xu
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Publication number: 20110113305Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.Type: ApplicationFiled: January 5, 2010Publication date: May 12, 2011Applicant: BroadLogic Network Technologies Inc.Inventors: Binfan Liu, Junyi Xu
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Patent number: 7809094Abstract: A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.Type: GrantFiled: October 15, 2007Date of Patent: October 5, 2010Assignee: BroadLogic Network Technologies Inc.Inventors: Junyi Xu, Binfan Liu, Vladimir Radionov, Weimin Zhang
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Patent number: 7720147Abstract: An MPEG processor is provided. According to one aspect of the processor, multiple MPEG data streams for corresponding channels are individually stored in an off-chip memory. Corresponding data for a channel is then retrieved from the off-chip memory for processing. The retrieved data is then decoded. The decoded results and associated information are stored on the off-chip memory. Some or all of the associated information that can be used for decoding subsequent data is stored in an on-chip memory. When video images need to be displayed, the corresponding data that is needed for that purpose is then retrieved from the off-chip memory and provided to an analog encoder for encoding in a format that is compatible with an analog display device.Type: GrantFiled: July 9, 2004Date of Patent: May 18, 2010Assignee: BroadLogic Network Technologies, Inc.Inventors: Weimin Zhang, Binfan Liu, Zhongqiang Wang
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Patent number: 7710965Abstract: A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.Type: GrantFiled: November 23, 2004Date of Patent: May 4, 2010Assignee: Broadlogic Network Technologies Inc.Inventors: Binfan Liu, Thomas Ayers, Weimin Zhang
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Publication number: 20090096514Abstract: A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.Type: ApplicationFiled: October 15, 2007Publication date: April 16, 2009Applicant: BroadLogic Network Technologies Inc.Inventors: Junyi Xu, Binfan Liu, Vladimir Radionov, Weimin Zhang
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Patent number: 7424080Abstract: A system for providing jitter-free transmissions for demodulated data streams is disclosed. In one embodiment, the system includes a demodulator, a packet processor and a timing generator. The demodulator further includes a timing recovery circuit. Output signals from the timing recovery circuit and demodulated output signals from the demodulator are provided to the timing generator. Using these signals, the timing generator then generates an output timing signal. Demodulated data are provided to the packet processor as input. The demodulated data are then output by the packet processor under the control of the output timing signal from the timing generator.Type: GrantFiled: July 31, 2003Date of Patent: September 9, 2008Assignee: Broadlogic Network Technologies, Inc.Inventor: Binfan Liu
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Publication number: 20060136768Abstract: A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.Type: ApplicationFiled: November 23, 2004Publication date: June 22, 2006Applicant: BroadLogic Network Technologies Inc.Inventors: Binfan Liu, Thomas Ayers, Weimin Zhang
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Patent number: 7065696Abstract: A system for providing a high-speed implementation for multi-stream forward error correction (FEC) is provided. According to one exemplary aspect, the system is able to provide block-based multi-stream FEC that reduces the power consumption when compared with conventional symbol-based FEC. The system provides a pipeline architecture for multi-stream FEC so that modules in the system are able to respectively process blocks of data from different channels or data streams.Type: GrantFiled: April 11, 2003Date of Patent: June 20, 2006Assignee: BroadLogic Network Technologies Inc.Inventors: Binfan Liu, Zhongqian Wang, Weimin Zhang
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Patent number: 7051171Abstract: A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write accesses to the SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The data bus length of the SDRAM is designed to be twice the deinterleaving symbol size thereby allowing bandwidth to be increased. The deinterleaver accesses data in the SDRAM as read blocks and write blocks. Each block includes a predetermined number of data words to be interleaved/deinterleaved. The ACTIVE command for one block is issued when a preceding block is being processed. Data in one read/write block has the same row address within the same bank of the SDRAM.Type: GrantFiled: April 11, 2003Date of Patent: May 23, 2006Assignee: BroadLogic Network Technologies, Inc.Inventors: Binfan Liu, Zhongqiang Wang, Thomas Ayers
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Publication number: 20050031042Abstract: An MPEG processor is provided. According to one aspect of the processor, multiple MPEG data streams for corresponding channels are individually stored in an off-chip memory. Corresponding data for a channel is then retrieved from the off-chip memory for processing. The retrieved data is then decoded. The decoded results and associated information are stored on the off-chip memory. Some or all of the associated information that can be used for decoding subsequent data is stored in an on-chip memory. When video images need to be displayed, the corresponding data that is needed for that purpose is then retrieved from the off-chip memory and provided to an analog encoder for encoding in a format that is compatible with an analog display device.Type: ApplicationFiled: July 9, 2004Publication date: February 10, 2005Applicant: BroadLogic Network Technologies Inc.Inventors: Weimin Zhang, Binfan Liu, Zhongqiang Wang