Patents by Inventor Bin Huang

Bin Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240373767
    Abstract: A method includes forming a first electrode layer on a substrate; depositing a transition metal layer on the first electrode layer, introducing a chalcogen precursor around the transition metal layer; performing a plasma treatment to ionize the chalcogen precursor around the transition metal layer to convert the transition metal layer into a transition metal dichalcogenide (TMDC) layer at a temperature lower than about 400° C.; forming a second electrode layer on the TMDC layer.
    Type: Application
    Filed: May 2, 2023
    Publication date: November 7, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Yu-Ting HUANG, Zih-Syuan HUANG, Jin-Bin YANG, I-Chih NI, Chih-I WU
  • Publication number: 20240371322
    Abstract: Provided is a display substrate. A data writing circuit included in each pixel circuit is coupled to a first scanning line, a switching control line, a data signal line, and a drive circuit. The data writing circuit transmits, under the control of the first scanning line and the switching control line, a data signal provided by the data signal line to the drive circuit, such that the drive circuit drives the coupled light-emitting element to emit light. In the same pixel circuit group, each pixel circuit subgroup is coupled to a different switching control line, and the plurality of coupled data signal lines are coupled to the same data line to receive the data signals from the data line. Thus, each pixel circuit, under the control of the switching control line coupled thereto, receives the data signal provided by the data line for the data signal line coupled thereto.
    Type: Application
    Filed: March 23, 2022
    Publication date: November 7, 2024
    Inventors: Zuwei WENG, Bin WENG, Yupeng HUANG, Bao LIU, Qiaohong HUANG
  • Publication number: 20240371540
    Abstract: Described herein are systems and methods for assembling electron spin and charge to possess one or more properties of a magnetic monopole. Example systems can include a laser configured to generate a light beam with a first spin and/or a first orbital angular momentum, and a surface including a coupling structure having a geometrical charge. When exposed to the light beam, the surface is configured to enable excitations of surface plasmon polariton field waves at metal-dielectric interfaces of the coupling structure to generate a plasmonic field. The surface can be configured to focus the plasmonic field to form a plasmonic vortex, in which plasmonic spin-orbit coupling between a total spin and a total orbital angular momentum forms a topological spin texture that is homotopic to that of a magnetic monopole.
    Type: Application
    Filed: April 22, 2022
    Publication date: November 7, 2024
    Inventors: Hrvoje Petek, Yanan Dai, Chen-Bin Huang, Atreyie Ghosh, Zhikang Zhou
  • Publication number: 20240372366
    Abstract: A response interaction system for intelligently interacting with a low-voltage user includes: a distribution network and system master station, an intelligent electric meter, a mobile APP, an intelligent interaction terminal, an intelligent gateway, and a low-voltage user load. In the process of the low-voltage user participating in the demand response, the distribution network and system master station publishes a demand response plan and a demand response notification through the mobile APP, the low-voltage user receives the demand response plan and the demand response notification through the mobile APP, the low-voltage user is connected to the intelligent interaction terminal through the mobile APP and controls a load to operate or not operate through the intelligent gateway, to perform the demand response task.
    Type: Application
    Filed: August 19, 2022
    Publication date: November 7, 2024
    Applicants: GUANGXI POWER GRID CO., LTD., ELECTRIC POWER RESEARCH INSTITUTE, CHINA SOUTHERN POWER GRID
    Inventors: Wenqian JIANG, Bin QIAN, Xiuqing LIN, Kun ZHANG, Zhou YANG, Jun CHEN, Keying HUANG, Jianlin TANG, Jueyu CHEN, Junli HUANG, Fan ZHANG, Zhitao TANG, Daiyuan BAO, Dandan YAN
  • Publication number: 20240372158
    Abstract: A secondary battery, a battery module, a battery pack, and an electrical device are disclosed. The secondary battery includes a positive electrode plate including a positive electrode film layer, a negative electrode plate including a negative electrode film layer, an electrolytic solution, and a solid electrolyte; the solid electrolyte is disposed on a surface of the positive and/or negative electrode film layer and includes a polymer matrix and a first additive, and the first additive is configured to form an interface film on the surface of the positive and/or negative electrode film layer, where a mass percentage of the polymer matrix relative to a total mass of the solid electrolyte is denoted as A %; and a mass percentage of the first additive relative to the total mass of the solid electrolyte is denoted as B %, and the secondary battery satisfies 0.1?B/A?19.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Huiling CHEN, Changlong HAN, Zeli WU, Jie GUO, Bin JIANG, Lei HUANG, Cuiping ZHANG
  • Publication number: 20240369642
    Abstract: A method and system for evaluating power battery aging state and screening retirement, wherein the method includes: performing first-level screening according to appearance and voltage data of a power battery; obtaining charging test data in a set time of the power battery subjected to the first-level screening, performing derivation and secondary derivation based on a capacity-voltage curve of the battery, respectively extracting a first index and a second index of a set peak of the derivated curve, and respectively using the first index and the second index to determine a battery category and consistency, thereby realizing second-level screening; and performing third-level screening on the battery subjected to the second-level screening based on a direct current internal resistance of the battery. By using the method and system, the detection time can be effectively reduced, the screening test cost can be reduced and the evaluation and screening precision can be improved.
    Type: Application
    Filed: October 17, 2022
    Publication date: November 7, 2024
    Applicant: SHANDONG UNIVERSITY
    Inventors: Bin DUAN, Peng HUANG, Chenghui ZHANG, Yongzhe KANG, Yunlong SHANG
  • Publication number: 20240370625
    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ruey-Bin SHEEN, Tien-Chien Huang, Chuan-Yao Tan
  • Publication number: 20240371688
    Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Yu-Shih Wang, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Chia-Cheng Chen, Liang-Yin Chen, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 12136566
    Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Shih Wang, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Chia-Cheng Chen, Liang-Yin Chen, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20240364390
    Abstract: Aspects for enabling Multiple-Input-Multiple-Output (MIMO) communications using a plurality of transmitters across at least two supported frequency bands are disclosed. The apparatus may be a user equipment (UE) that includes, for each UE-supported frequency band, a plurality of transmitters capable when configured of coherently transmitting the received information over the frequency band with information to be transmitted to a base station. The apparatus can identify MIMO coherence capability information for the supported frequency bands on a per-band and a per-band combination basis. The apparatus may determine a proposed transmission configuration based on the MIMO capability information and may report, to the base station, the proposed transmission configuration.
    Type: Application
    Filed: October 2, 2021
    Publication date: October 31, 2024
    Inventors: Yiqing CAO, Peter GAAL, Masato KITAZOE, Yi HUANG, Gokul SRIDHARAN, Alberto RICO ALVARINO, Bin HAN
  • Patent number: 12133417
    Abstract: The disclosure relates to the technical field of display, in particular to a displaying substrate, a manufacturing method thereof and a display panel. The displaying substrate comprises a passivation layer (28) and a flat layer (29) covering the passivation layer (28), wherein the flat layer (29) comprises a first flat via hole and a plurality of second flat via holes, the passivation layer (28) comprises a first passivation via hole, and the first flat via hole and the first passivation via hole form a first sleeve hole (31); and the hole depth of the first flat via hole is smaller than that of each second flat via hole, and the hole depth of the first passivation via hole is greater than or equal to the difference between the maximum hole depth of all the second flat via holes and the hole depth of the first flat via hole.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: October 29, 2024
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Leilei Cheng, Yongchao Huang, Qinghe Wang, Yang Zhang, Bin Zhou
  • Patent number: 12131580
    Abstract: A face detection method includes: acquiring a target image; invoking a face detection network, and processing the target image by using a feature extraction structure of the face detection network, to obtain original feature maps corresponding to the target image; the original feature maps having different resolutions; processing the original feature maps by using a feature enhancement structure of the face detection network, to obtain an enhanced feature map corresponding to each original feature map; the feature enhancement structure being obtained by searching a search space, and the search space used for searching the feature enhancement structure being determined based on a detection objective of the face detection network and a processing object of the feature enhancement structure; and processing the enhanced feature map by using a detection structure of the face detection network, to obtain a face detection result of the target image.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: October 29, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Jian Li, Bin Zhang, Yabiao Wang, Jinlong Peng, Chengjie Wang, Jilin Li, Feiyue Huang, Yongjian Wu
  • Publication number: 20240355258
    Abstract: A method for driving a display panel, and a display apparatus. An example of the method includes: receiving display data of an image to be displayed of the current display frame; and according to the display data, controlling a display panel to sequentially load a gate-on signal to gate lines, and to input a voltage into a data line, and when there is an overlap time between gate-on signals loaded to M adjacent gate lines, a pre-charging voltage and a compensation voltage are sequentially charged to a sub-pixel electrically connected to an Mth gate line among the M gate lines within the overlap time, M being an integer and M?2.
    Type: Application
    Filed: November 17, 2021
    Publication date: October 24, 2024
    Inventors: Qiaohong HUANG, Zuwei WENG, Bin WENG, Yupeng HUANG, Bao LIU
  • Publication number: 20240353758
    Abstract: Methods and systems for assembling electron spin and charge to possess one or more properties of a topological plasmonic spin texture array for performing lithography that is not limited by an optical system's diffraction limit are disclosed. According to one embodiment, the method includes defining a polarization of an optical field of light and a corresponding coupling-structure geometry. The method includes providing a coupling structure having the defined coupling-structure geometry in a metallic material, the coupling structure defining a region of the metallic material. The method includes directing light having the defined polarization to a center of the region, forming a lattice of plasmonic merons having a finer contrast resolution than a diffraction or reflection based resolution determined by Abbe limit based on the defined polarization of the optical field.
    Type: Application
    Filed: August 19, 2022
    Publication date: October 24, 2024
    Inventors: Hrvoje Petek, Zhikang Zhou, Atreyie Ghosh, Sena Yang, Tianyi Wang, Chen-Bin Huang, Yanan Dai
  • Publication number: 20240353095
    Abstract: A gas-fired steam-injection boiler has a flue and a water supply pipeline. The flue is provided with a radiation section and a convection section. The water supply pipeline has, in the flue gas flow direction, a first pipe section located at an upstream portion of the convection section, a second pipe section is located at a downstream portion of the convection section, and a third pipe section arranged between the first pipe section and the second pipe section. In a water flow direction of the water supply pipeline, the second pipe section, the first pipe section and the third pipe section are arranged in sequence. By using a flue gas condenser, the temperature of flue gas can be further reduced, and the latent heat of vaporization of steam in the flue gas is absorbed to form condensate water.
    Type: Application
    Filed: May 30, 2022
    Publication date: October 24, 2024
    Inventors: Jun CHEN, Naifeng ZHANG, Xuezhan ZHAO, Bo MA, Gang XIAO, Bin YANG, Qingjun SHANG, Zhihong HUANG, Yue ZHANG, Yong LI, Chao CHEN, Linlin JIANG
  • Publication number: 20240355680
    Abstract: A method for manufacturing a semiconductor device includes forming one or more work function layers over a semiconductor structure. The method includes forming a hardmask layer over the one or more work function layers. The method includes forming an adhesion layer over the hardmask layer. The method includes removing a first portion of a patternable layer that is disposed over the hardmask layer. The adhesion layer comprises an organic acid that concurrently bonds metal atoms of the hardmask layer and phenol groups of the patternable layer, thereby preventing an etchant from penetrating into a second portion of the patternable layer that still remains over the hardmask layer.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Chou, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20240355622
    Abstract: An integrated circuit device includes a substrate, a first transition metal dichalcogenide layer over the substrate, a dielectric layer over the first transition metal dichalcogenide layer, a first gate electrode, and a first source contact and a first drain contact. The first transition metal dichalcogenide layer has a surface roughness greater than 0.5 nm and less than 1 nm. The first gate electrode is over the dielectric layer and a first portion of the first transition metal dichalcogenide layer. The first source contact and the first drain contact are respectively connected with a second portion and a third portion of the first transition metal dichalcogenide layer. The first portion of the first transition metal dichalcogenide layer is between the second and third portions of the first transition metal dichalcogenide layer.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Ting CHANG, Jian-Zhi HUANG, Jin-Bin YANG, I-Chih NI, Chih-I WU
  • Patent number: 12127358
    Abstract: A middle frame includes an inner frame, a blocking member, and a covering member. The inner frame includes an outer surface and an inner surface opposite the outer surface. The inner frame further comprises at least one mounting hole penetrating the outer surface and the inner surface, the at least one mounting hole comprises an opening at the outer surface. The covering member covers the outer surface, and the blocking member is disposed between the covering member and the outer surface so as to cover the opening of the at least one mounting hole at the outer surface. An electronic device including the middle frame and a method for manufacturing the middle frame are also provided.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: October 22, 2024
    Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wen-Bin Huang, Hsiu-Fu Li, Je-Wei Chiang, Yi-Ren Fang, Yu-Cheng Zhang, Yu-Jen Chuang
  • Patent number: 12125890
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: October 22, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Publication number: 20240347955
    Abstract: A terminal module includes an insulating block, a ground terminal and a number of signal terminals. The ground terminal includes a number of first parts and at least one second part. Each first part includes a first fixing portion and a first tail portion. The second part includes a connecting portion and a number of first elastic contact arms. The connecting portion connects the number of first parts in series. Each signal terminal includes a second fixing portion, a second elastic contact arm and a second tail portion. The first elastic contact arm is configured to abut against a first ground conductive pad, and the second elastic contact arm is configured to abut against a first signal conductive pad. An electrical connector having the terminal module is also disclosed.
    Type: Application
    Filed: November 16, 2023
    Publication date: October 17, 2024
    Applicant: DONGGUAN LUXSHARE TECHNOLOGIES CO., LTD
    Inventors: Bin HUANG, Hongji CHEN, Kunlin YAO, Chuanqi GONG