Abstract: A method for manufacturing a semiconductor device includes forming a metal-including layer over a semiconductor substrate; forming a hydrophobic polymer layer over the metal-including layer; and forming an amphiphilic polymer layer between the metal-including layer and the hydrophobic polymer layer so as to enhance a bonding force therebetween.

Abstract: A comparator has a hysteresis value which is adjustable in response to a hysteresis setting control signal. An input of the comparator receives a modulated signal contaminated by in-band noise. A pulsed signal output from the comparator is converted by a digital to analog converter circuit an analog signal. That analog signal is converted by an analog to digital converter to a digital signal value. A comparison circuit compares the digital signal value to a threshold value and generates the hysteresis setting control signal to adjust the hysteresis value of the comparator in response to a result of the comparison in order to suppress the in-band noise from the output of the pulsed signal output from the comparator.

Abstract: An etchant for etching a cobalt-containing member in a semiconductor structure includes a fluorine-free acid and an alkaline solution, a rate of etching a cobalt-containing member by the etchant is greater than a rate of etching a nitride-containing member by the etchant, and a level of dissolved oxygen of the etchant is less than or equal to 100 ppb. A semiconductor structure, includes a plurality of epitaxial structures over a substrate, a gate structure over the substrate and between two of the plurality of epitaxial structures; a cobalt-containing member over one of the epitaxial structures and adjacent to the gate structure; and a dielectric member over the cobalt-containing member, wherein a top surface of the cobalt-containing member is formed by etching a portion of the cobalt-containing member using an etchant including a fluorine-free acid and an alkaline solution.

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Abstract: Disclosed is a method for estimating ultrasound attenuation coefficient by use of aberration compensation and the reference phantom method. Measurements on a human sample at a single transmit frequency and on multiple reference phantoms at a plurality of transmit frequencies are performed respectively. The center frequencies of the echo signals at the depth of the top edge of the region of interest are calculated. A specific reference phantom at a specific transmit frequency is selected by the echo signals whose center frequencies are closest to the center frequencies of the echo signals from the human sample at the aforementioned depth to compensate for the aberration. Then the spectra of the echo signals from the selected reference phantom at the selected transmit frequency and the spectra from the echo signals from the human sample are used to estimate the attenuation coefficient of the human sample by following the reference phantom method.

Abstract: A method for manufacturing a semiconductor device includes forming one or more work function layers over a semiconductor structure. The method includes forming a hardmask layer over the one or more work function layers. The method includes forming an adhesion layer over the hardmask layer. The method includes removing a first portion of a patternable layer that is disposed over the hardmask layer. The adhesion layer comprises an organic acid that concurrently bonds metal atoms of the hardmask layer and phenol groups of the patternable layer, thereby preventing an etchant from penetrating into a second portion of the patternable layer that still remains over the hardmask layer.

Abstract: A connector assembly includes a metal shielding cage and a heat dissipation plate. The metal shielding cage includes a first shell portion, a second shell portion and a receiving groove. The first shell portion includes a first receiving cavity configured to receive a first mating connector. The second shell portion includes a second receiving cavity configured to receive a second mating connector. The first shell portion and the second shell portion are configured to be mounted on a circuit board along a third direction. The third direction is perpendicular to the circuit board. The heat dissipation plate is inserted into the receiving groove along the third direction. The heat dissipation plate is configured to perform heat exchange with at least the first mating connector and the second mating connector.

Abstract: A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. A first wet etching process is performed by using a first etching solution, to clean a surface of the metal layer, wherein the first etching solution contains a base and a first oxidant. At least one cycle is performed. Each cycle includes a second wet etching process and a cleaning process. The second wet etching process is performed by using a second etching solution, to remove the metal layer, wherein the second etching solution contains an acid and a second oxidant. A cleaning process is performed.

Abstract: An electrical connector includes an insulating body, a number of first conductive terminals, a number of second conductive terminals, and a number of cables. The first conductive terminals include a number of first signal terminals and a number of first ground terminals. The second conductive terminals include a number of second signal terminals and a number of second ground terminals. The cables include a number of first cables electrically connected with the first signal terminals and a number of second cables electrically connected with the second signal terminals. The first ground terminals and the second ground terminals are connected to each other and are adapted to be electrically connected to a circuit board. With this arrangement, the present disclosure avoids ground return through cables, thereby simplifying the grounding method and improving the stability of signal transmission. The present disclosure also discloses an electrical connector assembly having the electrical connector.

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

Abstract: A kinetic sculpture and an intelligent control system are provided which comprise a plurality of movable bases (500), and the movable bases are arranged radially along a circumferential direction around a centerline disposed vertically; a bearing unit (400) is mounted on each of the movable bases (500), a vertical column (100) is mounted on the bearing unit (400), and a blade unit (200) is disposed on the column (100); the bearing units (400) move the columns (100) along the moving paths on the respective movable bases toward the position of the centerline or away from the position of the centerline to achieve combination or separation; the column systems correspondingly control each of the columns (100) to move. The kinetic sculpture enables the blades (201) of the kinetic sculpture to present a contour shape in gathered and separated states.

Abstract: An electrical connector includes an insulating body, a number of first conductive terminals and a number of second conductive terminals. Each first conductive terminal includes a first mating arm. Each second conductive terminal includes a second mating arm and a second press-fit portion for being mounted to a circuit board. Among the second conductive terminals, the second press-fit portions corresponding to any two adjacent second mating arms are disposed alternately along a second arrangement direction of the second mating arms. Therefore, it effectively avoids the mutual influence between the second press-fit portions, and facilitates the realization of the installation with the circuit board. The present disclosure also discloses an electrical connector assembly having the electrical connector.

Abstract: A data access method includes a target storage node that determines at least one data access policy input or selected by a user on a management platform. The target storage node receives a first write data stream from a request client, where the first write data stream indicates a first tape, first data to be written into the first tape, and first tape space required by the first data, the first tape space belongs to a same data partition. The target storage node writes the first data into the first tape according to the at least one data access policy using a first tape drive in at least one tape drive.

Abstract: Disclosed are a hopper, a slurry laying device, and a floor tile laying robot. The hopper includes a hopper body, a slurry mixing chamber is formed in the hopper body, a feeding port is provided at the top of the slurry mixing chamber, a slurry outlet is provided at the bottom of the slurry mixing chamber, the hopper body is further connected to at least two window structures communicated with the slurry mixing chamber, and an upper end opening of each window structure is arranged higher than a top wall of the slurry mixing chamber.

Abstract: The invention provides a porous polyurethane polishing pad that includes a porous matrix having large pores that extend upward from a base surface and open to an upper surface. The large pores extend to the top polishing surface and have lower and upper sections with a vertical orientation. The lower and upper sections are offset in a horizontal direction. Middle-sized pores with a columnar shape and a vertical orientation originate adjacent the middle sections and small pores with a columnar shape and a vertical orientation originate between the middle-sized pores. The pores combine for increasing compressibility of the polishing pad and contact area of the top polishing surface during polishing.

Abstract: An integrated nucleic acid processing apparatus includes a first operation area, a second operation area and a separation wall. The first operation area includes multiple carrying boards for placing objects and reagents for processing nucleic acids in samples, and multiple operation modules for performing operations of nucleic acid processing. The second operation area includes two extraction regions for respectively performing nucleic acid extractions. The separation wall separates the first operation area from the second operation area and includes two openable door sheets spatially corresponding to the two extraction regions. Nucleic acid extraction plates can be moved from the first operation area to the second operation area by means of the carrying boards as the two openable door sheets are opened, and be isolated in the second operation area for performing nucleic acid extractions as the two openable door sheets are closed.

Abstract: A gear fault diagnosis method based on joint weighted envelope noise-resistant correlation of sub-signals, comprising: converting an original vibration signal sequence into an envelope signal through a signal sequence element-wise squaring-low-pass filtering-square root computation process, reconstructing the envelope signal according to different time intervals to obtain a series of sub-signals, calculating a fault information representation measure of each sub-signal based on an L-moment theoretical index, assigning a weight to each sub-signal with Sigmoid transformation, calculating a joint weighted envelope noise-resistant correlation function of the envelope signal sequence and the reconstructed sub-signals based on the envelope signal, the reconstructed sub-signals and the corresponding weights thereof, and determining a characteristic frequency according to a reciprocal of a time interval value corresponding to the characteristic peak in a plot of the joint weighted envelope noise-resistant correlation

Abstract: A gear fault diagnosis method based on joint weighted envelope noise-resistant correlation of sub-signals, comprising: converting an original vibration signal sequence into an envelope signal through a signal sequence element-wise squaring-low-pass filtering-square root computation process, reconstructing the envelope signal according to different time intervals to obtain a series of sub-signals, calculating a fault information representation measure of each sub-signal based on an L-moment theoretical index, assigning a weight to each sub-signal with Sigmoid transformation, calculating a joint weighted envelope noise-resistant correlation function of the envelope signal sequence and the reconstructed sub-signals based on the envelope signal, the reconstructed sub-signals and the corresponding weights thereof, and determining a characteristic frequency according to a reciprocal of a time interval value corresponding to the characteristic peak in a plot of the joint weighted envelope noise-resistant correlation