Patents by Inventor Bin Li

Bin Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10499867
    Abstract: The present disclosure relates to a method, storage medium, and system for analyzing an image sequence of a periodic physiological activity. In one implementation, the method includes receiving the image sequence acquired by an imaging device, the image sequence having a plurality of frames and determining local motions for pixels in each frame of the image sequence. The local motion for a pixel may be determined using corresponding pixels in frames adjacent to the frame to which the pixel belongs. The method further includes determining principal motions for the plurality of frames based on the local motions; determining a motion magnitude profile based on the principal motions; and determining the phase of each frame in the image sequence based on the motion magnitude profile.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 10, 2019
    Assignee: SHENZHEN KEYA MEDICAL TECHNOLOGY CORPORATION
    Inventors: Xiaoxiao Liu, Shubao Liu, Bin Ma, Kunlin Cao, Youbing Yin, Yuwei Li, Qian Zhao, Qi Song
  • Patent number: 10505674
    Abstract: A polar code generation method and device are disclosed. The method includes: determining an index set of information bits of a polar code according to a first modulation scheme; and encoding the polar code according to the index set of the information bits of the polar code.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 10, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hui Shen, Bin Li
  • Patent number: 10505671
    Abstract: Disclosed in embodiments of the present disclosure are a polar code encoding method and device. The method includes: utilizing a common information bit set to represent each of m polar code blocks, the polar codes in each polar code block having the same code length and different code rates, and m being greater than or equal to 2; according to the common information bit set corresponding to the polar code block, acquiring an information bit set corresponding to each polar code in the polar code block; and according to the information bit set corresponding to each polar code in the polar code block, conducting polar code encoding on information to be encoded, thus reducing polar code representation overhead, and solving the problem in the prior art of excessively high polar code representation overhead.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 10, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hui Shen, Bin Li, Jun Chen
  • Patent number: 10506254
    Abstract: Innovations in the use of base color index map (“BCIM”) mode during encoding and/or decoding simplify implementation by reducing the number of modifications made to support BCIM mode and/or improve coding efficiency of BCIM mode. For example, some of the innovations involve reuse of a syntax structure that is adapted for transform coefficients to instead signal data for elements of an index map in BCIM mode. Other innovations relate to mapping of index values in BCIM mode or prediction of elements of an index map in BCIM mode. Still other innovations relate to handling of exception values in BCIM mode.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: December 10, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bin Li, Feng Wu, Jizheng Xu
  • Publication number: 20190372604
    Abstract: Embodiments of the present disclosure provide an encoding/decoding method, apparatus, and system. The method includes: encoding information bits to obtain a first-level encoded code word; obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present disclosure is applicable to various communication systems.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 5, 2019
    Inventors: Bin LI, Hui SHEN
  • Publication number: 20190371895
    Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a semiconductor region disposed adjacent to the substrate, first fin(s) disposed adjacent to the semiconductor region, first gate region(s) disposed adjacent to the first fin(s), first drain contact(s) disposed above the first fin(s), first source contact(s) disposed below the substrate, a second fin disposed above the semiconductor region, and a second gate region, second source contact and second drain contact disposed adjacent to the second fin and above the semiconductor region. First path(s) are formed between the first drain contact(s) and the first source contact(s) for current flow(s) through the first fin(s) in a vertical direction along the first path(s). A second path is formed between the second source contact and the second drain contact for current flow through the second fin in a horizontal direction along the second path.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 5, 2019
    Inventors: Xia LI, Gengming TAO, Bin YANG
  • Publication number: 20190372603
    Abstract: A network device polar encodes data to obtain a first encoded bit sequence, wherein the first encoded bit sequence comprises: bits in even number locations in the first encoded bit sequence and bits in odd number locations in the first encoded bit sequence; then the device interleaves the first encoded bit sequence to obtain an interleaved bit sequence; finally, the device rate matches the interleaved bit sequence and outputs the bit sequence after rate matched, wherein bits in even number locations of the interleaved bit sequence are from the bits in even number locations of the first encoded bit sequence, bits in odd number locations of the interleaved bit sequence are from the bits in odd number locations of the first encoded bit sequence.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Inventors: Hui SHEN, Bin LI, Jun CHEN
  • Publication number: 20190372251
    Abstract: The present invention provides a high-speed connector on a high density MINI version chip side, which comprises a board end connector, a wire end connector and a printed circuit board; the board end connector is arranged on the printed circuit board; the board end connector comprises a board end connector shell and a board end connector body arranged in the board end connector shell; the wire end connector comprises a wire end case and a tongue plate fixed to the wire end case; wherein at least one guide piece is extended from the board end connector shell, and the wire end case is provided with at least one guide slot for creating a butt joint with the guide piece. The connector of the present invention utilizes the space of the board end to the maximum extent, solves the problem that the CPU occupies the space of the board end due to the increased size of the heat dissipation module, and can realize high-speed data transmission.
    Type: Application
    Filed: April 29, 2019
    Publication date: December 5, 2019
    Applicant: LUXSHARE PRECISION INDUSTRY Co., Ltd.
    Inventors: Bin HUANG, Tiesheng LI, Hongji CHEN, Kun LIU
  • Publication number: 20190365867
    Abstract: A highly glycosylated human blood-clotting factor VIII (FVIII) fusion protein, and a manufacturing method and application of same. The fusion protein comprises, from the N-terminus to the C-terminus, a human (FVIII), a flexible peptide connector, at least one rigid unit of a human chorionic gonadotropin ?-subunit carboxyl terminal peptide, and a half-life extending portion (preferentially selected from a human IgG Fc variant). The fusion protein has a similar level of biological activity as a recombinant (FVIII) and an extended in vivo half-life, thereby improving pharmacokinetics and drug efficacy.
    Type: Application
    Filed: November 16, 2016
    Publication date: December 5, 2019
    Inventors: Qiang LI, Wenchen ZHU, Yuanli LI, Chenggong ZHU, Yongjuan GAO, Zijia REN, Luyan ZHU, Naichao SUN, Xiaoshan WANG, Bin LIU, Zhi LI, Wenwen WANG, Ming JIANG, Qilei WANG, Lirui WANG, Shuya WANG, Songlin ZHU, Jie GAO, Hongsheng SU
  • Publication number: 20190368800
    Abstract: A refrigerator, comprising: a refrigerator body, an air duct assembly and a branched air supply apparatus; the air duct assembly has an accommodating cavity, air passages, and air supply ports opening forward; the air passages comprise a first air passage and a plurality of second air passages; the branched air supply apparatus is installed in the accommodating cavity and has a peripheral wall portion; the peripheral wall portion defines a plurality of air outlets, the plurality of air outlets comprising a first air outlet and a plurality of second air outlets; the first air passage is communicated with the first air outlet and a first storage space; each second air passage is communicated with one second air outlet and one or more air supply ports, and each of the second air outlets communicates with at least one second air passage.
    Type: Application
    Filed: June 28, 2018
    Publication date: December 5, 2019
    Inventors: XUELI CHENG, BIN FEI, YAZHOU SHANG, DENGQIANG LI
  • Publication number: 20190371082
    Abstract: A three-dimensional virtual image display method is provided for a terminal. The method includes obtaining a first model map and a second model map of a three-dimensional virtual image, and determining a target region of the three-dimensional virtual image. The three-dimensional virtual image comprises a first model and a second model, and the target region is a joining region of the first model and the second model. The method also includes setting brightness of each pixel point in the target region in a shader to be a same value, the shader being configured to set illumination environmental data of each pixel point in the three-dimensional virtual image and the illumination environmental data at least comprising the brightness; and rendering the first model map and the second model map through the shader, so that a brightness of each pixel point in the target region displayed after rendering is equal.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Jinhui GUO, Hui CHEN, Bin LI
  • Publication number: 20190370530
    Abstract: In a method for facial feature point tracking, facial feature points of a face in a previous image of a to-be-tracked image are acquired in an image sequence. Facial feature point errors between the to-be-tracked image and the previous image are determined based on a preset error model and pixels in the to-be-tracked image. The facial feature point errors indicate differences between first coordinates of facial feature points in the to-be-tracked image, and second coordinates of facial feature points at corresponding positions in the previous image. The preset error model is trained based on facial feature points in a plurality of pairs of adjacent reference images. Further, the facial feature points of the face in the to-be-tracked image are determined based on the facial feature points of the face in the previous image and the facial feature point errors between the to-be-tracked image and the previous image.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Mengran LIN, Xinliang WANG, Bin LI
  • Publication number: 20190366420
    Abstract: A constructing-and-forging method for preparing homogenized forged pieces comprises: preparing preformed billets: cutting off a plurality of continuous casting billets, milling and smoothing surfaces of the billets to be welded, performing vacuum plasma cleaning operation to the surfaces to be welded, stacking the plurality of billets and sealing around the surfaces in a vacuum chamber by electron beam welding; forge-welding and homogenizing the preformed billets: heating the preformed billets to a certain temperature in a heating furnace and taking the heated preformed billets out of the heating furnace, forging the preformed billets by a hydraulic press, then using three-dimensional forging to disperse the welded surfaces such that composition, structure and inclusion of the interface areas are at the same level as those of the bodies of the billets. Cheap continuous casting billets are stacked and forge welded.
    Type: Application
    Filed: July 18, 2019
    Publication date: December 5, 2019
    Inventors: Mingyue SUN, Bin XU, Dianzhong LI, Yiyi LI
  • Publication number: 20190369568
    Abstract: With regard to a learning method for a smartwatch to prevent a metal hand from lightening the screen by unintended touch, a mainboard chip firstly finds and learns points which unintendedly touch the screen. Then, the mainboard chip reserves the time Tm which leads to unintended touch on the screen. The mainboard chip judges the present state: at the reserved time Tm, if the display screen is in an ON state, the display screen will keep the ON state. If the display screen is in an OFF state, the display screen will keep the OFF state.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Inventors: Fei Xiang, Bin Li, Caican Lin, Rui Xiao, Wei Gu, Xiaogao Zhou, Guang Yang, Lijun Qiao
  • Patent number: 10497813
    Abstract: An array substrate, preparation method thereof, display panel and display device are provided. The array substrate includes a base substrate and a plurality of thin film transistors distributed on the base substrate in an array. Each thin film transistor includes: a light-shielding block formed on the base substrate and provided with a first groove of which an opening direction is away from the base substrate; a buffer layer formed on one side of the light-shielding block away from the base substrate, a region of the buffer layer corresponding to the first groove being disposed with a second groove of which an opening direction is away from the base substrate; and a channel layer formed in the second groove. The structure uses bulges on two sides of the first groove to shield the light rays in regions without the thin film transistor, thereby improving the stability of the thin film transistor.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 3, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jun Liu, Wei Li, Bin Zhou, Tongshang Su, Jingang Fang, Yang Zhang
  • Patent number: 10494377
    Abstract: A compound having the formula (I): is disclosed. A method of preparing the compound of formula (I) is also disclosed.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: December 3, 2019
    Assignee: SHAANXI UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Bin Tian, Xingke Ju, Lei Tian, Jie Li, Songsong Ruan, Minyi Jia, Danni Tian, Han Li, Qianqian Zhao, Xuechuan Wang, Chengyuan Liang
  • Patent number: 10498229
    Abstract: A method to soft start a charge pump circuit according to embodiments includes enabling switching for a plurality of power transistors, selecting a first switching control signal from a plurality of switching control signals for the selected plurality of power transistors, slowly ramping up a plurality of bootstrap supply voltages associated with the selected plurality of power transistors, driving a gate-to-source voltage of each power transistor of the selected plurality of power transistors at a first predefined level, and determining if the plurality of bootstrap supply voltages are less than a second predefined level. If the plurality of bootstrap supply voltages are less than the second predefined level, the method further includes toggling and thereby selecting a second switching control signal from the plurality of switching control signals for a second selected plurality of power transistors.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 3, 2019
    Assignee: Intersil Americas LLC
    Inventors: Eric Magne Solie, Mehul Shah, Bin Li, Paul K. Sferrazza
  • Publication number: 20190361219
    Abstract: A switch element, an array substrate, a display panel, and a display device are disclosed. The switch element includes: a first electrode, an insulation layer, where the first electrode is located on a first side of the insulation layer; a second electrode and a third electrode arranged spaced from each other, both of which are located on a second side of the insulation layer away from the first electrode; and a first oil ink located between the second electrode and the third electrode, where the first oil ink is electrically conductive, and configured to connect or disconnect the second electrode with or from the third electrode under control of the first electrode.
    Type: Application
    Filed: August 24, 2017
    Publication date: November 28, 2019
    Inventors: Jincheng Gao, Xiaolong HE, Zhanfeng CAO, Bin ZHANG, Qi YAO, Zhengliang LI, Xuefei SUN, Wei ZHANG
  • Publication number: 20190357679
    Abstract: The present invention discloses a storage device and a refrigerator having the same. The storage device comprises a body, a pair of guiding mechanisms and a first partition frame, wherein the pair of guiding mechanisms is arranged at a pair of side walls of the body and comprises guiding elements which slide back and forth with respect to the body; the first partition frame comprises a partition element, fixing portions and a limited portion, the fixing portions are provided to be long rods extending in a front-rear direction and are formed at two ends of the first partition frame; the first partition frame is connected onto the guiding element by the fixing portion, and the limiting portion is fitted and connected with the limited portion, such that the first partition frame is prevented from moving back and forth with respect to the guiding element.
    Type: Application
    Filed: November 15, 2018
    Publication date: November 28, 2019
    Inventors: DENGQIANG LI, BIN FEI, YAZHOU SHANG, XUELI CHENG
  • Publication number: 20190363198
    Abstract: Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a first semiconductor region having a first doping type, a second semiconductor region having a second doping type different from the first doping type, a third semiconductor region disposed between the first semiconductor region and the second semiconductor region, a first terminal disposed adjacent to the first semiconductor region, a second terminal disposed adjacent to the second semiconductor region, and a third terminal disposed above the third semiconductor region. The first semiconductor region, the second semiconductor region, and/or the third semiconductor region include gallium nitride. The third semiconductor region includes multiple semiconductor layers having different materials.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 28, 2019
    Inventors: Gengming TAO, Xia LI, Bin YANG, Periannan CHIDAMBARAM