Abstract: The present disclosure discloses memory controllers, operation methods thereof, and memory systems. The memory controller comprises: a first buffer configured to buffer a valid data table and mapping information to be updated, wherein the valid data table is to record a plurality of valid transmission unit counts, the valid transmission unit count indicates the number of transmission units that store valid data in a corresponding block, the mapping information to be updated comprises at least one piece of mapping information from a logical address to a physical address, and each transmission unit corresponds to one physical address; a second buffer configured to buffer a mapping table, wherein the mapping table is to record a plurality of pieces of mapping information; and an acceleration processing circuit configured to: update the mapping table based on the mapping information; and update the valid data table based on the mapping information to be updated.

Abstract: A new transistor structure for use with III-Nitride semiconductor structures is disclosed. This transistor adds a top cap layer, etch stop layer and bottom cap layer between the gate electrode and the barrier layer. This structure enables a fabrication process in which the barrier layer is not subjected to plasma etching, which is a cause of etch related variations. In some embodiments, the bottom cap layer and optionally the etch stop layer extend from the source electrode to the drain electrode. A gate dielectric layer may optionally be included between the gate electrode and the top cap layer.

Abstract: The present application relates to a seat assembly and an adjustable armrest assembly. An adjustable armrest assembly may include an armrest mount, an armrest, and an armrest adjuster. The armrest may be adjustably connected to the armrest mount. The armrest adjuster may be pivotably connected to the armrest and the armrest mount. The armrest adjuster may be pivotably connectable to a seat of a seat assembly. The armrest adjuster may adjust the armrest relative to the armrest mount to (i) an extended position when said seat is adjusted to a first seat position and (ii) a retracted position when said seat is adjusted to a second seat position.

Abstract: The present disclosure discloses a measurement and diagnostic system for weight-bearing lines of lower limbs. The measurement and diagnostic system includes a data loading module, a keypoint selection module, an angle calculation module and a mechanical axis diagnosis and output module, wherein the angle calculation module is configured to calculate slopes among keypoints by using obtained keypoints, characteristic axes and joint lines, and calculate mechanical lateral distal femoral angles, joint line convergence angles, medial proximal tibial angles and lateral distal tibial angles by inverse trigonometric functions; and the mechanical axis diagnosis and output module is configured to compare the obtained angle values with preset values to judge whether a lower limb deformity occurs. The present disclosure further discloses an intelligent measurement method for weight-bearing lines of both lower limbs. The precise coordinates of the keypoints are not required in the present disclosure.

Abstract: Provided are a granulation-promoting microcarrier for an anaerobic ammonium oxidation (Anammox) process, and a preparation and use method thereof. The granulation-promoting microcarrier for the Anammox process is prepared by mixing a functional component, a regulatory component, and a structural component; wherein the functional component is an iron-based material; the regulatory component is a phase-change material; and the structural component includes a framework material and a foaming agent.

Abstract: A method and system for individualized target localization for transcranial magnetic stimulation (TMS) in treating depression. The system acquires resting-state functional MRI (R-fMRI) brain imaging data from subjects in both a major depressive disorder (MDD) group and a matching normal control group, followed by data preprocessing. Taking the spherical subgenual anterior cingulate cortex (sgACC) as the seed point, functional connectivity calculations are performed for each subject, and sgACC functional connectivity maps within the mask of the dorsolateral prefrontal cortex (DLPFC) region are extracted. A two-sample t-test is conducted on the sgACC functional connectivity maps of the two groups to identify clusters within the DLPFC mask that show significant differences between the two groups, which are used as group-level localization targets.

Abstract: According to embodiments of the disclosure, a method, system, device, medium and product for video processing are provided. The method includes extracting a plurality of feature maps from a plurality of frames of a video respectively; determining a plurality of frame-level features of a video instance in the plurality of frames based on the plurality of feature maps respectively, a frame-level feature in each of the frames representing feature information of the video instance in the frame; determining a video-level feature of the video instance by aggregating the plurality of frame-level features, the video-level feature representing feature information of the video instance across the plurality of frames; and determining an analysis result for the video instance in the plurality of frames based at least on the video-level feature.

Abstract: This disclosure describes the structure and technology to modify the free electron density between the anode electrode and cathode electrode of III-nitride semiconductor diodes. Electron density reduction regions (EDR regions) are disposed between the anode and cathode electrodes of the diode structure. In certain embodiments, the EDR regions are created using trenches. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. In another embodiment, a cap layer may be formed in the EDR regions, and doped regions may be created outside of the EDR regions, wherein the impurities act as electron donors.

Abstract: A semiconductor device includes a gate structure, a drift region, a source region, a drain region, a first doped region, and a second doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The first doped region is in the drift region and between the drain region and the gate structure. The second doped region is within the drift region. The second doped region forms a P-N junction with the first doped region at a bottom surface of the first doped region.

Abstract: The present disclosure generally relates to a personalized cancer vaccine having attenuated cancer cells transfected with at least one expression construct. The expression construct is capable of secretory expression of an antigenic polypeptide that could be derived from a protein from a virus. The personalized tumor vaccine, when administered to a subject in need thereof, is effective to activate an immune response.

Abstract: A semiconductor device includes a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The doped region is in the drift region and between the drain region and the gate structure. From a top view the doped region has a strip pattern extending in parallel with a strip pattern of the gate structure.

Abstract: A distributed fiber-optic acoustic sensing system and a signal processing method. The distributed fiber-optic acoustic sensing system is based on a high spatial resolution distributed fiber-optic acoustic sensor. The interval between adjacent sensing units is centimeter or millimeter level. Through specific digital signal processing, signal enhancement can be realized, noise in the system and environment are suppressed, at the same time, problems such as interference fading is solved, and the sensor signal-to-noise ratio of subunits can be increased by two to three orders of magnitude. Each subunit can serve as an independent high-sensitivity sensor for sensing. The multiple subunits can form one or more new sensor arrays. The azimuth estimation and spatial orientation of signal sources can be realized by the array signal processing method.

Abstract: The present disclosure provides a method for generating a backbone network, an apparatus for generating a backbone network, a device, and a storage medium. The method includes: acquiring a set of a training image, a set of an inference image, and a set of an initial backbone network; training and inferring, for each initial backbone network in the set of the initial backbone network, the initial backbone network by using the set of the training image and the set of the inference image, to obtain an inference time and an inference accuracy of a trained backbone network in an inference process; determining a basic backbone network based on the inference time and the inference accuracy of the trained backbone network in the inference process; and obtaining a target backbone network based on the basic backbone network and a preset target network.

Abstract: A capacitor includes: a semiconductor substrate; at least one trench provided in the semiconductor substrate and formed downward from an upper surface of the semiconductor substrate; a first conductive layer provided above the semiconductor substrate and in the trench; a first insulating layer provided between the substrate and the first conductive layer to isolate the first conductive layer from the substrate; a second conductive layer provided above the r substrate and in the trench, the second conductive layer including a first and a second conductive region that are independent from each other, the first conductive region being electrically connected to the substrate, and the second conductive region being electrically connected to the first conductive layer; and a second insulating layer provided between the first and the second conductive layer to isolate the first conductive region from the first conductive layer and isolate the second conductive region from the substrate.

Abstract: This disclosure describes the structure and technology to modify the free electron density between the gate and drain electrodes of III-nitride semiconductor transistors. Electron density reduction regions (EDR regions) are disposed between the gate and the drain of the transistor structure. In certain embodiments, the EDR regions are created using trenches. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. In another embodiment, a cap layer may be formed in the EDR regions, and doped regions may be created outside of the EDR regions, wherein the impurities act as electron donors.

Abstract: A surface-mounted high-speed permanent magnet synchronous rotor includes a rotor shaft, multiple permanent magnet sets, multiple silicon steel piece sets and a rotor iron core sleeve. The multiple permanent magnet sets and the multiple silicon steel piece sets are glued on a surface of the rotor shaft along an axis of the rotor shaft. The multiple permanent magnet sets and the multiple silicon steel piece sets are spaced around the rotor shaft. The multiple permanent magnet sets have a same outer diameter as the multiple silicon steel piece sets, and the multiple permanent magnet sets and the multiple silicon steel piece sets are sleeved with the rotor iron core sleeve.

Abstract: Provided are compositions comprising polynucleotides encoding modified MFT polypeptides. Also provided are recombinant DNA constructs, plants, plant cells, seed, and grain comprising the polynucleotides. Additionally, methods using the polynucleotides in plants to increase seed oil and/or protein content are also provided herein.

Abstract: This disclosure describes the structure of a transistor that provides improved performance by reducing the off-state capacitance between the source and the drain by using a cap layer to extend the electrical distance between the gate and the source and drain contacts. In certain embodiments, a dielectric layer may be disposed between the gate electrode and the cap layer and vias are created in the dielectric layer to allow the gate electrode to contact the cap layer at select locations. In some embodiments, the gate electrode is offset from the cap layer to allow a more narrow cap layer and to allow additional space between the gate electrode and the drain contact facilitating the inclusion of a field plate. The gate electrode may be configured to only contact a portion of the cap layer.