Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: Systems and methods for monitoring and controlling repetitive accesses to a dynamic random-access memory (DRAM) row are disclosed. A method for monitoring and controlling repetitive accesses to a DRAM can include dividing a bank of the DRAM into a number of logical blocks, mapping each row of the bank to one of the logical blocks, monitoring accesses to the logical blocks, and controlling accesses to the logical blocks based on the monitoring.

Abstract: Systems, methods, and other embodiments associated with tracking packet identifiers are described. According to one embodiment, a method includes receiving a packet of data that includes an encoded packet identifier and decoding the encoded packet identifier into a decoded packet identifier. The method further includes estimating a reliability of the decoded packet identifier and determining a packet identifier of the received packet based, at least in part, on the estimated reliability of the decoded packet identifier.

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation.

Abstract: Aspects of the disclosure provide a method. The method includes boosting a portion of frequency components of a digital signal that is converted from an analog signal based on a clock signal, generating a decision signal based on the boosted digital signal, generating a timing error signal based on the boosted digital signal and the decision signal, and filtering the timing error signal to generate a voltage signal to control a voltage controlled oscillator to generate the clock signal.

Abstract: A timing jitter measurement circuit for measuring timing jitter in the digital domain may use an interpolator bank to over-sample a signal from a media reader, a zero crossing estimator to estimate a zero crossing moment in the output of the interpolator bank and a time interval analyzer (TIA) to calculate the timing jitter as the deviation of the estimated zero crossing moment from an expected zero crossing moment in a clock signal. The timing jitter measurement circuit may be integrated into digital circuitry since it avoids using analog devices. Consequently, it may simplify the chip design, lower power consumption and save space.

Abstract: Methods and systems for compensating reducing jitter produced by a phase-locked loop are disclosed. For example, in a particular embodiment, a phase-locked loop device for reducing jitter may include a voltage-control oscillator (VCO) signal configured to produce a VCO signal, phase-detection circuitry configured to compare an input signal and the VCO signal to produce a phase error signal, and slew-rate limiting circuitry configured to receive the phase error signal and apply a slew-rate limit process on the phase error signal to produce a modified error signal.

Abstract: Aspects of the disclosure provide a signal processing circuit. The signal processing circuit includes a processing path and a zero-start module. The processing path is configured to process an electrical signal that is generated in response to reading data on a storage medium. The data includes at least a first field and a second field. The electrical signal has a first profile corresponding to the first field and has a second profile corresponding to the second field. The zero-start module is configured to detect a field change from the first field to the second field, and control the processing path to add a compensation as a function of a profile change from the first profile to the second profile to keep the processed electrical signal to have a predetermined profile in response to the detected field change.

Abstract: A method of managing delivery of content to end users of an application executing on an application server is disclosed. A definition of a first variant of a web page is received, the definition of the first variant specifying that an instance of a first widget is to be included in the first variant at a first region conforming to a page layout of the web page. A definition of a second variant of the web page is received, the definition of the second variant specifying that an instance of a second widget is to be included in the second variant at a second region conforming to the page layout of the web page. A comparison of the first variant and the second variant is presented with respect to a performance metric, the performance metric pertaining to an effectiveness of the web page at bringing in revenues to a network-based publication system.

Abstract: An integrated circuit includes a first memory, a second memory, a processor, and a descrambler. The first memory is configured to store a key. The first memory is a one-time-programmable memory. The processor is configured to: determine whether the first memory has been programmed; and in response to the first memory not having been programmed, (i) load firmware from a third memory into the second memory, and (ii) execute the firmware. The third memory is separate from the integrated circuit. The processor is also configured to, in response to the first memory having been programmed, load the firmware from the third memory into the second memory. The descrambler is configured to, in response to the first memory having been programmed, descramble the firmware based on the key.

Abstract: Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation.

Abstract: A method of managing delivery of content to end users of an application executing on an application server is disclosed. A definition of a first variant of a web page is received, the definition of the first variant specifying that an instance of a first widget is to be included in the first variant at a first region conforming to a page layout of the web page. A definition of a second variant of the web page is received, the definition of the second variant specifying that an instance of a second widget is to be included in the second variant at a second region conforming to the page layout of the web page. A comparison of the first variant and the second variant is presented with respect to a performance metric, the performance metric pertaining to an effectiveness of the web page at bringing in revenues to a network-based publication system.

Abstract: Systems, methods, and other embodiments associated with tracking packet identifiers are described. According to one embodiment, a method includes receiving packets of data, wherein each packet includes an encoded packet identifier, the encoded packet identifier being decoded into a decoded packet identifier, and after each packet is received, incrementing a first counter and a second counter for estimating a sequential value of the decoded packet identifier.

Abstract: A timing jitter measurement circuit for measuring timing jitter in the digital domain may use an interpolator bank to over-sample a signal from a media reader, a zero crossing estimator to estimate a zero crossing moment in the output of the interpolator bank and a time interval analyzer (TIA) to calculate the timing jitter as the deviation of the estimated zero crossing moment from an expected zero crossing moment in a clock signal. The timing jitter measurement circuit may be integrated into digital circuitry since it avoids using analog devices. Consequently, it may simplify the chip design, lower power consumption and save space.

Abstract: Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation.

Abstract: Methods and apparatus to provide a handheld pointer-based user interface are described herein. An example apparatus includes a wireless pointer component and one or more base components. The wireless pointer component is configured to transmit one or more human-computer interaction (HCI) signals associated with an HCI event via a first communication link. One or more base components are operatively coupled to a screen of a display to receive the one or more HCI signals from the wireless pointer component via the first communication link. Further, the one or more base components are configured to generate at least one of operating information and position information of the wireless pointer component based on the one or more HCI signals, and to transmit the at least one of operating information and position information to a processor configured to generate screen information on the screen of the display via a second communication link.

Abstract: A system-on-a-chip including a first one-time-programmable memory, a second memory, a test interface, an input circuit, and a processor. The input circuit is configured to receive data transmitted from a third memory to the system-on-a-chip. The processor is configured to, while booting up the system-on-a-chip, determine whether a first one-time-programmable memory has been previously programmed. The processor is also configured to (i) in response to the first one-time-programmable memory not having been previously programmed, enable the test interface for debugging of the system-on-a-chip, (ii) based on the first one-time-programmable memory having been previously programmed, disable the test interface, and (iii) subsequent to one of the enabling of the test interface and the disabling of the test interface, load the data from the third memory into the second memory.

Abstract: Aspects of the disclosure provide a method for signal processing. The method includes receiving a tracking signal corresponding to a recording track on a storage medium. The tracking signal is frequency modulated with encoded symbols. Further, the method includes phase-locking an internal signal to the tracking signal to cause a frequency of the internal signal to be locked at a center frequency of the tracking signal, detecting a drift between the internal signal and the encoded symbols, and phase-shifting the internal signal to compensate for the drift.

Abstract: A system-on-a-chip includes a first memory and a processor. The first memory is configured to store a boot code. The processor is configured to (i) access the first memory, and (ii) execute the boot code when booting up. The processor is configured to, while booting up, determine whether a first one-time-programmable memory has been previously programmed based on the boot code. The processor is configured to, in response to the first one-time-programmable memory not having been previously programmed based on the boot code, (i) load firmware from a second memory into a third memory, and (ii) execute the firmware loaded into the third memory. The processor is configured to, in response to the first one-time-programmable memory having been previously programmed, verify a digital signature of the firmware.