Abstract: A method for forming a semiconductor device is provided. A dielectric layer is formed on a substrate. First and second gate trenches are formed in the dielectric layer. First and second spacers are disposed in the first and the second gate trenches, respectively. A patterned photoresist is formed on the dielectric layer. The patterned photoresist masks the first region and exposes the second region. Multiple cycles of spacer trimming process are performed to trim a sidewall profile of the second spacer. Each cycle comprises a step of oxygen stripping and a successive step of chemical oxide removal. The patterned photoresist is then removed to reveal the first region.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, part of the MTJ stack is removed, a first cap layer is formed on a sidewall of the MTJ stack, and the first cap layer and the MTJ stack are removed to form a first MTJ and a second MTJ.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

Abstract: A cell structure of magnetoresistive RAM includes a synthetic anti-ferromagnetic (SAF) layer to serve as a pinned layer; a barrier layer, disposed on the SAF layer; and a magnetic free layer, disposed on the barrier layer. The SAF layer includes: a first magnetic layer; a second magnetic layer; and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first magnetic layer and the second magnetic layer interfacing with the spacer layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.

Abstract: A method of forming a resistive random access memory cell includes the following steps. A first electrode layer, a blanket resistive switching material layer and a second electrode layer are formed on a layer sequentially. The second electrode layer is patterned to form a second electrode. The blanket resistive switching material layer is patterned to form a resistive switching material layer. An oxygen implanting process is performed to implant oxygen in two sidewall parts of the resistive switching material layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a magnetic tunneling junction (MTJ) on the metal interconnection; forming a top electrode on the MTJ; and forming a trapping layer on the top electrode for trapping hydrogen. Preferably, the trapping layer includes a concentration gradient, in which a concentration of hydrogen decreases from a top surface of the top electrode toward the MTJ.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

Abstract: A method for forming a semiconductor device is provided. A dielectric layer is formed on a substrate. First and second gate trenches are formed in the dielectric layer. First and second spacers are disposed in the first and the second gate trenches, respectively. A patterned photoresist is formed on the dielectric layer. The patterned photoresist masks the first region and exposes the second region. Multiple cycles of spacer trimming process are performed to trim a sidewall profile of the second spacer. Each cycle comprises a step of oxygen stripping and a successive step of chemical oxide removal. The patterned photoresist is then removed to reveal the first region.

Abstract: A method for forming a semiconductor device is disclosed. A substrate having at least two fins thereon and an isolation trench between the at least two fins is provided. A liner layer is then deposited on the substrate. The liner layer conformally covers the two fins and interior surface of the isolation trench. A stress-buffer film is then deposited on the liner layer. The stress-buffer film completely fills a lower portion that is located at least below half of a trench depth of the isolation trench. A trench-fill oxide layer is then deposited to completely fill an upper portion of the isolation trench.

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part . The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.

Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate, forming a patterned layer on the substrate, the patterned layer comprising at least a trench formed therein, depositing a first dielectric layer on the patterned layer and sealing an air gap in the trench, depositing a second dielectric layer on the first dielectric layer and completely covering the patterned layer, and performing a curing process to the first dielectric layer and the second dielectric layer.