Abstract: Methods, systems, and devices for host system diagnostic testing are described. A diagnostic tool including a diagnostic executable stored to an external memory may evaluate a system including a host subsystem and a memory subsystem. Upon initialization, the diagnostic executable may configure trace points in one or more layers (e.g., associated with an operating system) of the host subsystem based on dependencies (e.g., libraries) stored to the external memory, and may receive, from the host subsystem, first data collected at the trace points, directly from a host system buffer, or from the memory subsystem. Concurrent to the collection procedure, the diagnostic executable may perform processing operations on the first data to generate second data, which may be associated with one or more metrics of system performance. The second data is stored to the external memory, and may be utilized to evaluate the system.

Abstract: In some implementations, a memory apparatus may receive, from a host system, a first read command indicating first data, wherein the first read command includes a read ahead indication. The memory apparatus may obtain, based on the first read command including the read ahead indication, second data from a non-volatile memory location. The memory apparatus may store the second data in a volatile memory location.

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

Abstract: Methods, systems, and devices for unified command transmission for managed memory are described. A host system may be configured to transmit a unified command transmission including multiple boot commands of a same type to a memory system for performing a boot procedure of the memory system. A bootloader (e.g., system startup software) may support generating the unified command transmission, such that a host command manager may transmit the unified command transmission to the memory system. The memory system may receive the unified command transmission and perform the boot operations associated with the unified command transmission. In some cases, performing the boot operations may include sequentially performing each boot operation for a single system interrupt. The memory system may transmit information associated with the boot operations back to the host command manager in a message, and the host command manager may transmit an indication of the message to the bootloader.

Abstract: The disclosure relates to improvements in command execution in semiconductor devices. In some aspects, the techniques described herein relate to an apparatus including: a storage array; and a processor configured to: receive a command from a host processor, start to profile the command by initializing a counter at a first time, issue the command to the storage array, receive a response to the command, end profiling of the command at a second time, and update a command timing for a type of the command.

Abstract: Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

Abstract: Methods, systems, and devices for host system diagnostic testing are described. A diagnostic tool including a diagnostic executable stored to an external memory may evaluate a system including a host subsystem and a memory subsystem. Upon initialization, the diagnostic executable may configure trace points in one or more layers (e.g., associated with an operating system) of the host subsystem based on dependencies (e.g., libraries) stored to the external memory, and may receive, from the host subsystem, first data collected at the trace points, directly from a host system buffer, or from the memory subsystem. Concurrent to the collection procedure, the diagnostic executable may perform processing operations on the first data to generate second data, which may be associated with one or more metrics of system performance. The second data is stored to the external memory, and may be utilized to evaluate the system.

Abstract: Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.

Abstract: Methods, systems, and devices for techniques to retire unreliable blocks are described. A memory system may receive a request for information about a quantity of erase operations performed on a block of the memory system. Based on the request, the memory system may determine the quantity of erase operations performed on the block and transmit an indication of the quantity of erase operations performed on the block.

Abstract: A method includes receiving a first read request during a first boot time. The first read request includes a logical block address and a length. The method also includes tracing the first read request. The method further includes creating a table using the traced first read request. The table includes a sequential record of each traced read request received during the first boot time. The method further includes transmitting the table to a host system during a second boot time. The method further includes receiving a second read request during the second boot time. The second read request includes a logical to physical representation obtained using the table and the logical block address.

Abstract: Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.

Abstract: Various embodiments enable sending a notification to a host system based on an address mapping entry miss (or mismatch) on a memory sub-system, which can facilitate an update of one or more address mapping entries stored on the host system.

Abstract: The disclosure relates to improvements in command execution in semiconductor devices. In some aspects, the techniques described herein relate to an apparatus including: a storage array; and a processor configured to: receive a command from a host processor, start to profile the command by initializing a counter at a first time, issue the command to the storage array, receive a response to the command, end profiling of the command at a second time, and update a command timing for a type of the command.

Abstract: Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

Abstract: Methods, systems, and devices for host side memory address management are described. In some examples, a host system may identify a read request that includes a logical address of a block of a memory device. The read request may be associated with a descriptor indicating a page of a cache of the host system. The host system may determine to assign a descriptor to a page of the cache, and may recycle one or more pages of the cache. In some examples, the host system may determine whether the page indicated by the descriptor includes a mapping between the logical address and a physical address of the memory device, and may issue a read command to the memory device based on the page including the mapping.

Abstract: Methods, systems, and devices for techniques to retire unreliable blocks are described. A memory system may receive a request for information about a quantity of erase operations performed on a block of the memory system. Based on the request, the memory system may determine the quantity of erase operations performed on the block and transmit an indication of the quantity of erase operations performed on the block.

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

Abstract: A computing system can comprise a processing resource and a memory device coupled together via a first transmission link. The processing resource can be configured to test the first transmission link in response to the memory device failing to execute a command by sending the command to the memory device again for retry and monitoring the first transmission link for signals that indicate whether the command was executed by the memory device.