Patents by Inventor Bindiganavale S. Nataraj

Bindiganavale S. Nataraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9349738
    Abstract: A content addressable memory (CAM) device can include a plurality of CAM cells each formed within a cell area of a substrate. Each cell area can have a cell length dimension in a first direction parallel to a substrate surface. The CAM device can also include at least one common line comprising a contiguous region of the substrate doped to a first conductivity type and formed in a base semiconductor region doped to a second conductivity type. The common line can extend in the first direction for more than one cell length and can be commonly coupled to non-power supply connections to the plurality of CAM cells.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: May 24, 2016
    Assignee: Broadcom Corporation
    Inventors: Bindiganavale S. Nataraj, Varadarajan Srinivasan
  • Patent number: 8982596
    Abstract: A CAM device includes a CAM array that can implement column redundancy in which a defective column segment in a selected block can be functionally replaced by a selected column segment of the same block, and/or by a spare column segment of the same block.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: March 17, 2015
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Bindiganavale S. Nataraj, Sandeep Khanna
  • Patent number: 8913412
    Abstract: A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and an incremental match line charge circuit. The detector circuit generates a feedback signal based on a detected match line voltage. The charge circuit partially pre-charges the match line to an intermediate voltage during a pre-charge phase of a compare operation, and then selectively charges the match line higher towards a supply voltage in response to the feedback signal.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: December 16, 2014
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Sandeep Khanna, Bindiganavale S. Nataraj, Varadarajan Srinivasan
  • Patent number: 8767488
    Abstract: A method and apparatus for performing half-column redundancy in a CAM device is disclosed, capable of replacing a defective half-column in the CAM array with only one half of another column. For example, present embodiments can provide twice the redundancy by replacing only one half of a defective CAM cell with one half of a spare cell or of a selected cell. The half-column redundancy disclosed herein provides finer granularity and higher effectiveness to the redundancy scheme as compared to conventional redundancy schemes employed on a CAM array. Thus, the CAM array can be designed and fabricated with a higher yield without having to accommodate for more spare columns than employed by conventional redundancy schemes, allowing for more efficient use of silicon area and a more robust CAM array design.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: July 1, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Sandeep Khanna, Bindiganavale S. Nataraj
  • Patent number: 8730704
    Abstract: A CAM device is disclosed that includes an array of CAM cells in which the compare circuits of groups of CAM cells are connected together using a conductive layer interposed between a polysilicon layer of the CAM device and the metal-1 layer of the CAM device. This allows the data lines (e.g., the bit lines and/or comparand lines) of the CAM array to be formed in the metal-1 layer of the CAM device, which in turn allows the match lines of the CAM array to be formed in the metal-2 layer of the CAM device. The conductive layer, which may be a silicide layer, is connected to the match line by a via extending from the conductive layer through the metal-1 layer to the metal-2 layer.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: May 20, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, John Zimmer, Sandeep Khanna, Vinay Iyengar, Chetan Deshpande
  • Patent number: 8324929
    Abstract: An integrated circuit device can include a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another. A configuration circuit can selectively connect each signal path to a corresponding one of a plurality of physical connection points to the IC device according to one of at least two different physical orders in response to configuration information.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: December 4, 2012
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Vinay Raja Iyengar, Venkat Rajendher Reddy Gaddam, Bindiganavale S. Nataraj
  • Patent number: 8089794
    Abstract: A method may include selectively coupling a result line to a reference node in response to a compare data value being applied to a plurality of compare cell circuits; precharging the result line to the precharge potential by enabling a first precharge path while the compare data value is being applied; and after precharging the result line by enabling the first precharge path, disabling the first precharge path to place it in a high impedance state.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: January 3, 2012
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Chetan Deshpande, Bindiganavale S. Nataraj
  • Patent number: 8031501
    Abstract: Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on a detected matching condition of another cell block. By selectively enabling cell blocks during search operations only when needed, energy consumption is reduced. Selectively enabling a cell block includes selectively pre-charging match lines to the cell block, selectively enabling word lines to the cell block, and selectively enabling comparand line to the cell block. In accordance with certain embodiments, the CAM device is configurable to perform search operations in a pipelined manner. Accordingly, the CAM device is capable of performing multiple search operations simultaneously.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: October 4, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, Chetan Deshpande, Vinay Iyengar, Sandeep Khanna
  • Patent number: 7943400
    Abstract: An semiconductor device having a plurality of fabrication layers. A first region of a first fabrication layer of the semiconductor device is revised. To signal the revision, a connectivity structure in a second region of the first fabrication layer is omitted to interrupt an otherwise continuous signal path that extends through a plurality of interconnection layers of the semiconductor device.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: May 17, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Bindiganavale S. Nataraj
  • Patent number: 7920398
    Abstract: A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and a pre-charge circuit. The detector circuit detects a voltage of the match line and generates a feedback signal based on the detected match line voltage. The pre-charge circuit adaptively charges the match line in response to the feedback signal.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: April 5, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Sandeep Khanna, Bindiganavale S. Nataraj, Chetan Deshpande, Vinay Iyengar
  • Patent number: 7920397
    Abstract: A memory device operates in a calibration mode during which the effects of bit line leakage current are measured and to operate in a normal mode during which the bit line current is adjusted to compensate for leakage according to the results of the calibration mode. In the calibration mode, a leakage-free sense operation is performed to determine the differential voltage generated on the bit lines in response to a data value. Then, a leakage-susceptible test read operation is performed to determine the differential voltage generated on the bit lines in response to the data value. A detection circuit measures the difference between the differential voltages generated in the leakage-free and leakage-susceptible test read operations to generate a compensation signal, which subsequently adjusts the bit line compensation current during the normal mode.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: April 5, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, Sandeep Khanna, Varadarajan Srinivasan
  • Patent number: 7920399
    Abstract: A content addressable memory (CAM) device includes a CAM array and a configuration circuit. The CAM array has a plurality of rows of CAM cells, each row segmented into a plurality of row segments, each row segment including a plurality of CAM cells coupled to a corresponding match line segment, and a match line control circuit having an input coupled to the corresponding match line segment, an output coupled to the match line segment in a next row segment, and a control terminal to receive a corresponding enable signal. The configuration circuit has an input to receive configuration information indicative of a width and depth configuration of the CAM array and having outputs to generate the enable signals.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: April 5, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, Vinay Iyengar, Chetan Deshpande, Sandeep Khanna
  • Patent number: 7868383
    Abstract: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: January 11, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Dimitri Argyres, Bindiganavale S. Nataraj
  • Patent number: 7848129
    Abstract: A content addressable memory (CAM) device includes a comparand register, a CAM array, and partition logic. The comparand register has inputs to receive a search key, and outputs coupled to the CAM array, which includes a plurality of individually selectable sub-arrays. Each sub-array includes a number of rows of CAM cells and a control circuit, wherein each row of CAM cells is coupled to a match line, and wherein the control circuit has an input to receive a corresponding sub-array enable signal. The partition logic has an input to receive a partition select signal, and is configured to generate the sub-array enable signals in response to the partition select signal. The control circuits selectively propagate the search key through the sub-arrays in response to the sub-array enable signals.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: December 7, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Chetan Deshpande, Vinay Iyengar, Bindiganavale S. Nataraj
  • Patent number: 7830691
    Abstract: A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: November 9, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Sandeep Khanna, Bindiganavale S. Nataraj
  • Patent number: 7800930
    Abstract: An integrated circuit device can include a plurality of compare cell circuits that selectively provide charge transfer path between a result line and a reference node according to a comparison between a stored data value and an applied compare data value during a compare time period. A first precharge circuit can have a controllable impedance path coupled between the result line and a precharge voltage node. A control circuit can place the first precharge circuit into a low impedance state during a first portion of the compare time period, and into a high impedance state during a second portion of the compare time period.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: September 21, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Chetan Deshpande, Bindiganavale S. Nataraj
  • Patent number: 7782084
    Abstract: An integrated circuit device can include a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another. A configuration circuit can selectively connect each signal path to a corresponding one of a plurality of physical connection points to the IC device according to one of at least two different physical orders in response to configuration information.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: August 24, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Vinay Raja Iyengar, Venkat Rajendher Reddy Gaddam, Bindiganavale S. Nataraj
  • Patent number: 7688609
    Abstract: A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in each of the plurality of rows of CAM cells, a plurality of timed storage circuits, each having a data input coupled to a corresponding match line and having an enable input coupled to an enable signal line, a timing generator configured to generate an enable signal on the enable signal line, and a plurality of load elements.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: March 30, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Bindiganavale S. Nataraj, Sandeep Khanna
  • Publication number: 20090250820
    Abstract: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.
    Type: Application
    Filed: June 12, 2009
    Publication date: October 8, 2009
    Inventors: Dimitri Argyres, Bindiganavale S. Nataraj
  • Patent number: 7589362
    Abstract: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: September 15, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Dimitri Argyres, Bindiganavale S. Nataraj