Abstract: This disclosure provides systems, methods, and devices for wireless communications that support enhanced phase calibration operations. In a first aspect, an apparatus for wireless communications includes a processing system. The processing system is configured to cause the wireless communication device to: receive a reference signal at a respective input of a plurality of receive chains; process, by each receive chain, the reference signal to generate a respective output signal; determine, for each receive chain, a phase alignment difference between the respective output signal of the receive chain and a reference output signal of a reference receive chain of the plurality of receive chains; and adjust a phase alignment of a divider of at least one receive chain of the plurality of receive chains based on the determined phase alignment difference for the at least one receive chain. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for wireless communications that support enhanced phase calibration operations. In a first aspect, an apparatus for wireless communications includes a processing system. The processing system is configured to cause the wireless communication device to: receive a reference signal at a respective input of a plurality of receive chains; process, by each receive chain, the reference signal to generate a respective output signal; determine, for each receive chain, a phase alignment difference between the respective output signal of the receive chain and a reference output signal of a reference receive chain of the plurality of receive chains; and adjust a phase alignment of a divider of at least one receive chain of the plurality of receive chains based on the determined phase alignment difference for the at least one receive chain. Other aspects and features are also claimed and described.

Abstract: Techniques for designing baseband processing circuitry for radio IC's. In an aspect, techniques for differential-to-single-ended conversion in a baseband portion of the IC are disclosed to reduce the pin count and package size for RF IC's. In another aspect, the converter includes selectable narrowband and wideband amplifiers, wherein the wideband amplifiers may be implemented using transistor devices having smaller area than corresponding transistor devices of narrowband amplifiers. Further techniques for bypassing one or more elements, and for implementing a low-pass filter of the converter using an R-C filter network, are described.

Abstract: Techniques for designing baseband processing circuitry for radio IC's. In an aspect, techniques for differential-to-single-ended conversion in a baseband portion of the IC are disclosed to reduce the pin count and package size for RF IC's. In another aspect, the converter includes selectable narrowband and wideband amplifiers, wherein the wideband amplifiers may be implemented using transistor devices having smaller area than corresponding transistor devices of narrowband amplifiers. Further techniques for bypassing one or more elements, and for implementing a low-pass filter of the converter using an R-C filter network, are described.

Abstract: An integrated circuit for transmit and receive matching is described. The integrated circuit includes a transmit amplifier. The transmit amplifier includes a first transistor, a second transistor and a first inductor. The first inductor couples the first transistor to the second transistor. The integrated circuit also includes a low noise amplifier. The low noise amplifier includes a third transistor, a fourth transistor, the first inductor, a second inductor, a third inductor and a transformer. The second inductor couples the first inductor to the third transistor. The third inductor couples the third transistor to ground.

Abstract: An integrated circuit for transmit and receive matching is described. The integrated circuit includes a transmit amplifier. The transmit amplifier includes a first transistor, a second transistor and a first inductor. The first inductor couples the first transistor to the second transistor. The integrated circuit also includes a low noise amplifier. The low noise amplifier includes a third transistor, a fourth transistor, the first inductor, a second inductor, a third inductor and a transformer. The second inductor couples the first inductor to the third transistor. The third inductor couples the third transistor to ground.

Abstract: A system and method for suppressing RFI receives a differential input signal Vd, and a signal Vcm which varies with the common mode component of Vd. Vcm is phase-shifted and then amplified with a programmable gain G1 to produce an output VA1. A subtractor produces an output Vsub which varies with Vd?VA1. Vsub is amplified with a programmable gain G2 to produce an output VA2. An analog input signal processing circuit receives VA2 at an input which has an associated maximum dynamic range. A processor adjusts G2 such that VA2 covers the maximum dynamic range, adjusts the phase shift and G1 to minimize VA2, and adjusts G2 to increase VA2 such that it again covers the maximum dynamic range. The RFI in Vd is substantially subtracted out, thereby enabling the full dynamic range of the analog input signal processing circuit to be employed in receiving Vd.

Abstract: A JFET switch select circuit including a first current mirror system including a first high current mirror circuit referenced to high rail voltage and a first low current mirror circuit referenced to a low rail voltage, a second current mirror system including a second high current mirror circuit referenced to the high rail voltage and a second low current mirror circuit referenced to the low rail voltage, and a comparator circuit responsive to an input voltage and a reference voltage for directing current from a current supply circuit to one of the first and second high current mirror circuits and one of the first and second low current mirror circuits for saturating a switching device of one of the first and second high current mirror circuits to set a first output voltage proximate to a high rail voltage and for saturating a switching device of one of the first and second low current mirror circuits to set a second output voltage proximate a low rail voltage.