Patents by Inventor Bindu Prabhakar Rao

Bindu Prabhakar Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Slave latch controlled retention flop with lower leakage and higher performance
    Patent number: 7652513
    Abstract: In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: January 26, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Bindu Prabhakar Rao, Sumanth Katte Gururajarao, Dharin N. Shah
  • Slave latch controlled retention flop with lower leakage and higher performance
    Publication number: 20090058484
    Abstract: In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.
    Type: Application
    Filed: August 27, 2007
    Publication date: March 5, 2009
    Inventors: Bindu Prabhakar Rao, Sumanth Katte Gururajarao, Dharin N. Shah