Abstract: A method of generating a first performance-data-library (for a standard-cell-library) includes: for each standard cell that includes multiple gates, sorting the gates into groups including searching for matched ones amongst the gates (matched gates), grouping corresponding matched gates into corresponding multiple member-gates, and (for unmatched ones of the gates having no other matched gate (unmatched gates)), grouping the unmatched gates into corresponding single-member groups; for each standard cell, generating a corresponding first volume of performance data including, for each group, discretely calculating the first volume of performance data, mapping the volume of performance data to the subject gate in the group, and, for each multimember group, mapping the volume of performance data to non-subject gates; and basing the first performance-data-library at least in part on the first volumes of performance data.

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.

Abstract: A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure, a metal-metal capacitor formed by at least a pair of metal electrodes on the same plane underneath the bonding pad structure, at least an interconnection metal layer, at least a via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract: A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each dielectric layer. The metal patterns disposed in each dielectric layer extend to the next underlying dielectric layer.

Abstract: A method of fabricating high resistivity thin film resistors. An isolation region is formed on a substrate to isolate the active regions. A polysilicon layer is formed above the substrate. A diffusion barrier layer is formed above the polysilicon layer. Lightly doped ions are implanted in the polysilicon layer. The substrate is annealed at a high temperature. The diffusion barrier layer and the polysilicon layer are patterned to form a high-resistive thin film resistor. Spacers are formed on the sidewalls of the high-resistive thin film resistor.

Abstract: A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.

Abstract: A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each dielectric layer. The metal patterns disposed in each dielectric layer extend to the next underlying dielectric layer.

Abstract: The invention relates to a method of blowing the fuse structure. The fuse formed in a substrate comprises a conductor and an insulating layer, which has uniform thickness and is formed on the conductor. The method of blowing fuse structure comprises the steps of cutting the insulating layer formed on the conductor, exposing the surface of the conductor and producing insulation by a chemical reaction.

Abstract: A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.

Abstract: A surface of a semiconductor substrate comprises at least one electrical conduction structure and at least one eFuse. The electrical conduction structure comprises a first poly silicon layer and a first poly silicide layer formed in the first poly silicon layer. The eFuse comprises a second poly silicon layer and a second poly silicide layer formed on the second poly silicon layer. The area of the second poly silicide layer is smaller than the area of the first poly silicide layer.

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract: A processing method for fabricating silicide is provided. First of all, a semiconductor structure having a semiconductor surface and an insulation surface is provided. Next, an epitaxial layer on the semiconductor surface is formed. And, the semiconductor structure is treated. The treat step is that the removal rate of the insulation surface is faster than the removal rate of the epitaxial layer. Then, a metal layer on the epitaxial layer is formed. Finally, heating the epitaxial layer forms silicide. The treatment step prevents the insulation surface from the formation of the silicide so as to reduce the degradation of device characteristics.

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure, a metal-metal capacitor formed by at least a pair of metal electrodes on the same plane underneath the bonding pad structure, at least an interconnection metal layer, at least a via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract: A semiconductor device comprising a substrate with an integrated circuit structure and a patterned metallic layer thereon is provided. The patterned metallic layer includes a first pattern and a second pattern. The first pattern has a thickness different from the second pattern. Since the first pattern and the second pattern on the substrate each has a thickness optimized for their respective use, performance of the semiconductor device is improved.

Abstract: A semiconductor device comprising a substrate with an integrated circuit structure and a patterned metallic layer thereon is provided. The patterned metallic layer includes a first pattern and a second pattern. The first pattern has a thickness different from the second pattern. Since the first pattern and the second pattern on the substrate each has a thickness optimized for their respective use, performance of the semiconductor device is improved.

Abstract: A semiconductor device comprising a substrate with an integrated circuit structure and a patterned metallic layer thereon is provided. The patterned metallic layer includes a first pattern and a second pattern. The first pattern has a thickness different from the second pattern. Since the first pattern and the second pattern on the substrate each has a thickness optimized for their respective use, performance of the semiconductor device is improved.

Abstract: A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.