Abstract: An adjustable voltage regulator circuit, including a voltage conversion circuit, a voltage conversion controller, and a clock generator, is provided. The voltage conversion circuit receives an input voltage to generate an output voltage. The voltage conversion controller detects the output voltage, compares the output voltage with a reference voltage value, and outputs an enable signal based on a comparison result to control the voltage conversion circuit to adjust the output voltage. The clock generator generates a first clock signal and a second clock signal to respectively drive the voltage conversion circuit and the voltage conversion controller. The voltage conversion controller adjusts the enable signal to gradually adjust the output voltage to a predetermined voltage range.

Abstract: A static random-access memory (SRAM) circuit and associated read operation method and write operation method are provided. The SRAM circuit includes memory units arranged in M columns and N rows, M bit lines, N row-voltage selection lines, N word lines, and a control circuit. The control circuit includes a controller, a voltage source, a voltage selection module, a word-line driving module, and a bit-line driving module. The voltage source provides a first voltage and a second voltage. When the control circuit performs access to the memory unit located in the mth column and the nth row, the voltage selection module transmits one of the first voltage and the second voltage to an nth row-voltage selection line. The voltage selection module transmits the second voltage to the other (N-1) row-voltage selection lines. The variables M, N, m, and n are positive integers.

Abstract: An error detection and correction method is provided. The method includes: when a pipeline stage error is detected, correcting the pipeline stage error; when it is determined that a plurality of cascaded pipeline stage circuits have continuous pipeline stage errors, stopping all operations of all pipeline stage circuits; flushing the data of the pipeline stage circuits; and re-processing the data of the pipeline stage circuits at a downclocked frequency.

Abstract: A switched-capacitor DC-DC voltage converter and a control method thereof. The switched-capacitor DC-DC voltage converter comprises at least one switch array, comprising a capacitor and at least one switch group, wherein the switch group comprises a plurality of power switches connected to one another in parallel, and one end of the capacitor is electrically connected to the switch group; and a control circuit, converting an input control signal into a control signal set, and outputting the control signal set to the switch group, and the control signal set comprises a plurality of control signals with phase delayed sequentially and the duty cycle reduced sequentially.

Abstract: A switched-capacitor DC-DC voltage converter and a control method thereof. The switched-capacitor DC-DC voltage converter comprises at least one switch array, comprising a capacitor and at least one switch group, wherein the switch group comprises a plurality of power switches connected to one another in parallel, and one end of the capacitor is electrically connected to the switch group; and a control circuit, converting an input control signal into a control signal set, and outputting the control signal set to the switch group, and the control signal set comprises a plurality of control signals with phase delayed sequentially and the duty cycle reduced sequentially.