Abstract: A memory device includes a plurality of memory cells located in a first region of the memory device. The memory cells include a first signal line, a first circuit located in the first region of the memory device, and a plurality of logic circuits located in a second region of the memory device. The second region and the first region have different design rules. The first circuit is configured to be selectively enabled and disabled. When the first circuit is enabled, the first signal line is electrically coupled in parallel with a second signal line.

Abstract: A memory device includes a plurality of memory cells located in a first region of the memory device. The memory cells include a first signal line, a first circuit located in the first region of the memory device, and a plurality of logic circuits located in a second region of the memory device. The second region and the first region have different design rules. The first circuit is configured to be selectively enabled and disabled. When the first circuit is enabled, the first signal line is electrically coupled in parallel with a second signal line.

Abstract: A dual-port SRAM includes a substrate, first and second active regions over the substrate and oriented lengthwise generally along a first direction; first and second gate electrodes oriented lengthwise generally along a second direction perpendicular to the first direction. The first and second gate electrodes engage the first and second active regions to form first and second pass gate transistors, respectively. The dual-port SRAM further includes a first gate contact disposed over the first gate electrode and electrically connected to the first gate electrode and a first source/drain contact oriented lengthwise generally along the second direction. The first source/drain contact directly contacts source/drain features of the first and second pass gate transistors. A portion of the first gate contact and a portion of the first source/drain contact are at a same vertical level from a top surface of the substrate and are aligned along the first direction.

Abstract: A dual-port SRAM includes a substrate, first and second active regions over the substrate and oriented lengthwise generally along a first direction; first and second gate electrodes oriented lengthwise generally along a second direction perpendicular to the first direction. The first and second gate electrodes engage the first and second active regions to form first and second pass gate transistors, respectively. The dual-port SRAM further includes a first gate contact disposed over the first gate electrode and electrically connected to the first gate electrode and a first source/drain contact oriented lengthwise generally along the second direction. The first source/drain contact directly contacts source/drain features of the first and second pass gate transistors. A portion of the first gate contact and a portion of the first source/drain contact are at a same vertical level from a top surface of the substrate and are aligned along the first direction.

Abstract: A device includes a memory bit cell and a retention circuit. The memory bit cell includes a first metal line and a second metal line. The first metal line is disposed in a first metal layer and configured to receive a retention voltage. The second metal line is disposed in the first metal layer and configured to receive a first reference voltage lower than the retention voltage. The retention circuit includes a third metal line. The third metal line is disposed in the first metal layer and configured to transmit the retention voltage to the first metal line. A distance between the second metal line and the third metal line is less than a length of the memory bit cell.

Abstract: A device includes a memory bit cell and a retention circuit. The memory bit cell includes a first metal line and a second metal line. The first metal line is disposed in a first metal layer and configured to receive a retention voltage. The second metal line is disposed in the first metal layer and configured to receive a first reference voltage lower than the retention voltage. The retention circuit includes a third metal line. The third metal line is disposed in the first metal layer and configured to transmit the retention voltage to the first metal line. A distance between the second metal line and the third metal line is less than a length of the memory bit cell.

Abstract: A device for fabricating an alignment layer includes a chamber, a conveying means, deposition device, and an ion beam alignment device. The conveying means is arranged in the chamber and serves to carry the substrate. The deposition device is arranged above the conveying means in the chamber and serves to form the layer. The ion beam alignment device is arranged above the conveying means in the chamber, and serves to perform the alignment of the layer. The deposition device and the ion beam alignment device can be replaced with an ion beam deposition/alignment device so that the formation and alignment of the layer can be performed in a chamber.